Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 98d88f873359e4961970485589df6caa382586e3 / . / arch / sandbox / dts / test.dts
blob: 1d011ded7cc0ec3bb79c8a17a7d81de9db3cd824 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]79 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]80 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]81 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]82 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]84 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]85 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
86 <0>, <&gpio_a 12>;
87 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
88 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
89 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]90 int-value = <1234>;
91 uint-value = <(-1234)>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]92 };
93
94 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]95 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]96 compatible = "not,compatible";
97 };
98
99 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]100 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]101 };
102
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]103 backlight: backlight {
104 compatible = "pwm-backlight";
105 enable-gpios = <&gpio_a 1>;
106 power-supply = <&ldo_1>;
107 pwms = <&pwm 0 1000>;
108 default-brightness-level = <5>;
109 brightness-levels = <0 16 32 64 128 170 202 234 255>;
110 };
111
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]112 bind-test {
113 bind-test-child1 {
114 compatible = "sandbox,phy";
115 #phy-cells = <1>;
116 };
117
118 bind-test-child2 {
119 compatible = "simple-bus";
120 };
121 };
122
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]123 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]124 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]125 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]126 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]127 ping-add = <3>;
128 };
129
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]130 phy_provider0: gen_phy@0 {
131 compatible = "sandbox,phy";
132 #phy-cells = <1>;
133 };
134
135 phy_provider1: gen_phy@1 {
136 compatible = "sandbox,phy";
137 #phy-cells = <0>;
138 broken;
139 };
140
141 gen_phy_user: gen_phy_user {
142 compatible = "simple-bus";
143 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
144 phy-names = "phy1", "phy2", "phy3";
145 };
146
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]147 some-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]150 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]151 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]152 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]153 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]154 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]155 compatible = "denx,u-boot-fdt-test";
156 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]157 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 ping-add = <5>;
159 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]160 c-test@0 {
161 compatible = "denx,u-boot-fdt-test";
162 reg = <0>;
163 ping-expect = <6>;
164 ping-add = <6>;
165 };
166 c-test@1 {
167 compatible = "denx,u-boot-fdt-test";
168 reg = <1>;
169 ping-expect = <7>;
170 ping-add = <7>;
171 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]172 };
173
174 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]176 ping-expect = <6>;
177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
181 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]182 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]183 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]184 ping-add = <6>;
185 compatible = "google,another-fdt-test";
186 };
187
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]188 f-test {
189 compatible = "denx,u-boot-fdt-test";
190 };
191
192 g-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]196 h-test {
197 compatible = "denx,u-boot-fdt-test1";
198 };
199
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]200 clocks {
201 clk_fixed: clk-fixed {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <1234>;
205 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]206 };
207
208 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]209 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]210 #clock-cells = <1>;
211 };
212
213 clk-test {
214 compatible = "sandbox,clk-test";
215 clocks = <&clk_fixed>,
216 <&clk_sandbox 1>,
217 <&clk_sandbox 0>;
218 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]219 };
220
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]221 eth@10002000 {
222 compatible = "sandbox,eth";
223 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]224 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]225 };
226
227 eth_5: eth@10003000 {
228 compatible = "sandbox,eth";
229 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]230 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]231 };
232
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]233 eth_3: sbe5 {
234 compatible = "sandbox,eth";
235 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]236 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]237 };
238
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]239 eth@10004000 {
240 compatible = "sandbox,eth";
241 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]242 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]243 };
244
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]245 firmware {
246 sandbox_firmware: sandbox-firmware {
247 compatible = "sandbox,firmware";
248 };
249 };
250
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]251 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]252 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]253 gpio-controller;
254 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]255 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]256 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]257 };
258
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]259 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]260 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]261 gpio-controller;
262 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]263 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]264 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]265 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]266
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]267 i2c@0 {
268 #address-cells = <1>;
269 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]270 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]271 compatible = "sandbox,i2c";
272 clock-frequency = <100000>;
273 eeprom@2c {
274 reg = <0x2c>;
275 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]276 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]277 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]278
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]279 rtc_0: rtc@43 {
280 reg = <0x43>;
281 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]282 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]283 };
284
285 rtc_1: rtc@61 {
286 reg = <0x61>;
287 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]288 sandbox,emul = <&emul1>;
289 };
290
291 i2c_emul: emul {
292 reg = <0xff>;
293 compatible = "sandbox,i2c-emul-parent";
294 emul_eeprom: emul-eeprom {
295 compatible = "sandbox,i2c-eeprom";
296 sandbox,filename = "i2c.bin";
297 sandbox,size = <256>;
298 };
299 emul0: emul0 {
300 compatible = "sandbox,i2c-rtc";
301 };
302 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]303 compatible = "sandbox,i2c-rtc";
304 };
305 };
306
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]307 sandbox_pmic: sandbox_pmic {
308 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]309 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]310 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]311
312 mc34708: pmic@41 {
313 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]314 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]315 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]316 };
317
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]318 bootcount@0 {
319 compatible = "u-boot,bootcount-rtc";
320 rtc = <&rtc_1>;
321 offset = <0x13>;
322 };
323
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]324 adc@0 {
325 compatible = "sandbox,adc";
326 vdd-supply = <&buck2>;
327 vss-microvolts = <0>;
328 };
329
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]330 lcd {
331 u-boot,dm-pre-reloc;
332 compatible = "sandbox,lcd-sdl";
333 xres = <1366>;
334 yres = <768>;
335 };
336
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]337 leds {
338 compatible = "gpio-leds";
339
340 iracibble {
341 gpios = <&gpio_a 1 0>;
342 label = "sandbox:red";
343 };
344
345 martinet {
346 gpios = <&gpio_a 2 0>;
347 label = "sandbox:green";
348 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]349
350 default_on {
351 gpios = <&gpio_a 5 0>;
352 label = "sandbox:default_on";
353 default-state = "on";
354 };
355
356 default_off {
357 gpios = <&gpio_a 6 0>;
358 label = "sandbox:default_off";
359 default-state = "off";
360 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]361 };
362
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]363 mbox: mbox {
364 compatible = "sandbox,mbox";
365 #mbox-cells = <1>;
366 };
367
368 mbox-test {
369 compatible = "sandbox,mbox-test";
370 mboxes = <&mbox 100>, <&mbox 1>;
371 mbox-names = "other", "test";
372 };
373
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]374 cpu-test1 {
375 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]376 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]377 };
378
379 cpu-test2 {
380 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]381 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]382 };
383
384 cpu-test3 {
385 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]386 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]387 };
388
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]389 i2s: i2s {
390 compatible = "sandbox,i2s";
391 #sound-dai-cells = <1>;
392 };
393
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]394 misc-test {
395 compatible = "sandbox,misc_sandbox";
396 };
397
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]398 mmc2 {
399 compatible = "sandbox,mmc";
400 };
401
402 mmc1 {
403 compatible = "sandbox,mmc";
404 };
405
406 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]407 compatible = "sandbox,mmc";
408 };
409
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]410 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]411 compatible = "sandbox,pci";
412 device_type = "pci";
413 #address-cells = <3>;
414 #size-cells = <2>;
415 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
416 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]417 pci@0,0 {
418 compatible = "pci-generic";
419 reg = <0x0000 0 0 0 0>;
420 emul@0,0 {
421 compatible = "sandbox,swap-case";
422 };
423 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]424 pci@1f,0 {
425 compatible = "pci-generic";
426 reg = <0xf800 0 0 0 0>;
427 emul@1f,0 {
428 compatible = "sandbox,swap-case";
429 };
430 };
431 };
432
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]433 pci1: pci-controller1 {
434 compatible = "sandbox,pci";
435 device_type = "pci";
436 #address-cells = <3>;
437 #size-cells = <2>;
438 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
439 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]440 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]441 0x0c 0x00 0x1234 0x5678
442 0x10 0x00 0x1234 0x5678>;
443 pci@10,0 {
444 reg = <0x8000 0 0 0 0>;
445 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]446 };
447
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]448 pci2: pci-controller2 {
449 compatible = "sandbox,pci";
450 device_type = "pci";
451 #address-cells = <3>;
452 #size-cells = <2>;
453 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
454 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
455 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
456 pci@1f,0 {
457 compatible = "pci-generic";
458 reg = <0xf800 0 0 0 0>;
459 emul@1f,0 {
460 compatible = "sandbox,swap-case";
461 };
462 };
463 };
464
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]465 probing {
466 compatible = "simple-bus";
467 test1 {
468 compatible = "denx,u-boot-probe-test";
469 };
470
471 test2 {
472 compatible = "denx,u-boot-probe-test";
473 };
474
475 test3 {
476 compatible = "denx,u-boot-probe-test";
477 };
478
479 test4 {
480 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]481 first-syscon = <&syscon0>;
482 second-sys-ctrl = <&another_system_controller>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]483 };
484 };
485
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]486 pwrdom: power-domain {
487 compatible = "sandbox,power-domain";
488 #power-domain-cells = <1>;
489 };
490
491 power-domain-test {
492 compatible = "sandbox,power-domain-test";
493 power-domains = <&pwrdom 2>;
494 };
495
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]496 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]497 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]498 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]499 };
500
501 pwm2 {
502 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]503 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]504 };
505
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]506 ram {
507 compatible = "sandbox,ram";
508 };
509
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]510 reset@0 {
511 compatible = "sandbox,warm-reset";
512 };
513
514 reset@1 {
515 compatible = "sandbox,reset";
516 };
517
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]518 resetc: reset-ctl {
519 compatible = "sandbox,reset-ctl";
520 #reset-cells = <1>;
521 };
522
523 reset-ctl-test {
524 compatible = "sandbox,reset-ctl-test";
525 resets = <&resetc 100>, <&resetc 2>;
526 reset-names = "other", "test";
527 };
528
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]529 rproc_1: rproc@1 {
530 compatible = "sandbox,test-processor";
531 remoteproc-name = "remoteproc-test-dev1";
532 };
533
534 rproc_2: rproc@2 {
535 compatible = "sandbox,test-processor";
536 internal-memory-mapped;
537 remoteproc-name = "remoteproc-test-dev2";
538 };
539
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]540 panel {
541 compatible = "simple-panel";
542 backlight = <&backlight 0 100>;
543 };
544
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]545 smem@0 {
546 compatible = "sandbox,smem";
547 };
548
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]549 sound {
550 compatible = "sandbox,sound";
551 cpu {
552 sound-dai = <&i2s 0>;
553 };
554
555 codec {
556 sound-dai = <&audio 0>;
557 };
558 };
559
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]560 spi@0 {
561 #address-cells = <1>;
562 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]563 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]564 compatible = "sandbox,spi";
565 cs-gpios = <0>, <&gpio_a 0>;
566 spi.bin@0 {
567 reg = <0>;
568 compatible = "spansion,m25p16", "spi-flash";
569 spi-max-frequency = <40000000>;
570 sandbox,filename = "spi.bin";
571 };
572 };
573
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]574 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]575 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]576 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]577 };
578
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]579 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]580 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]581 reg = <0x20 5
582 0x28 6
583 0x30 7
584 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]585 };
586
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]587 syscon@2 {
588 compatible = "simple-mfd", "syscon";
589 reg = <0x40 5
590 0x48 6
591 0x50 7
592 0x58 8>;
593 };
594
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]595 timer {
596 compatible = "sandbox,timer";
597 clock-frequency = <1000000>;
598 };
599
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]600 tpm2 {
601 compatible = "sandbox,tpm2";
602 };
603
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]604 uart0: serial {
605 compatible = "sandbox,serial";
606 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]607 };
608
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]609 usb_0: usb@0 {
610 compatible = "sandbox,usb";
611 status = "disabled";
612 hub {
613 compatible = "sandbox,usb-hub";
614 #address-cells = <1>;
615 #size-cells = <0>;
616 flash-stick {
617 reg = <0>;
618 compatible = "sandbox,usb-flash";
619 };
620 };
621 };
622
623 usb_1: usb@1 {
624 compatible = "sandbox,usb";
625 hub {
626 compatible = "usb-hub";
627 usb,device-class = <9>;
628 hub-emul {
629 compatible = "sandbox,usb-hub";
630 #address-cells = <1>;
631 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]632 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]633 reg = <0>;
634 compatible = "sandbox,usb-flash";
635 sandbox,filepath = "testflash.bin";
636 };
637
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]638 flash-stick@1 {
639 reg = <1>;
640 compatible = "sandbox,usb-flash";
641 sandbox,filepath = "testflash1.bin";
642 };
643
644 flash-stick@2 {
645 reg = <2>;
646 compatible = "sandbox,usb-flash";
647 sandbox,filepath = "testflash2.bin";
648 };
649
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]650 keyb@3 {
651 reg = <3>;
652 compatible = "sandbox,usb-keyb";
653 };
654
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]655 };
656 };
657 };
658
659 usb_2: usb@2 {
660 compatible = "sandbox,usb";
661 status = "disabled";
662 };
663
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]664 spmi: spmi@0 {
665 compatible = "sandbox,spmi";
666 #address-cells = <0x1>;
667 #size-cells = <0x1>;
668 pm8916@0 {
669 compatible = "qcom,spmi-pmic";
670 reg = <0x0 0x1>;
671 #address-cells = <0x1>;
672 #size-cells = <0x1>;
673
674 spmi_gpios: gpios@c000 {
675 compatible = "qcom,pm8916-gpio";
676 reg = <0xc000 0x400>;
677 gpio-controller;
678 gpio-count = <4>;
679 #gpio-cells = <2>;
680 gpio-bank-name="spmi";
681 };
682 };
683 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]684
685 wdt0: wdt@0 {
686 compatible = "sandbox,wdt";
687 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]688
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]689 axi: axi@0 {
690 compatible = "sandbox,axi";
691 #address-cells = <0x1>;
692 #size-cells = <0x1>;
693 store@0 {
694 compatible = "sandbox,sandbox_store";
695 reg = <0x0 0x400>;
696 };
697 };
698
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]699 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]700 #address-cells = <1>;
701 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]702 chosen-test {
703 compatible = "denx,u-boot-fdt-test";
704 reg = <9 1>;
705 };
706 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]707
708 translation-test@8000 {
709 compatible = "simple-bus";
710 reg = <0x8000 0x4000>;
711
712 #address-cells = <0x2>;
713 #size-cells = <0x1>;
714
715 ranges = <0 0x0 0x8000 0x1000
716 1 0x100 0x9000 0x1000
717 2 0x200 0xA000 0x1000
718 3 0x300 0xB000 0x1000
719 >;
720
721 dev@0,0 {
722 compatible = "denx,u-boot-fdt-dummy";
723 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]724 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]725 };
726
727 dev@1,100 {
728 compatible = "denx,u-boot-fdt-dummy";
729 reg = <1 0x100 0x1000>;
730
731 };
732
733 dev@2,200 {
734 compatible = "denx,u-boot-fdt-dummy";
735 reg = <2 0x200 0x1000>;
736 };
737
738
739 noxlatebus@3,300 {
740 compatible = "simple-bus";
741 reg = <3 0x300 0x1000>;
742
743 #address-cells = <0x1>;
744 #size-cells = <0x0>;
745
746 dev@42 {
747 compatible = "denx,u-boot-fdt-dummy";
748 reg = <0x42>;
749 };
750 };
751 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]752
753 osd {
754 compatible = "sandbox,sandbox_osd";
755 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]756
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]757 board {
758 compatible = "sandbox,board_sandbox";
759 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]760
761 sandbox_tee {
762 compatible = "sandbox,tee";
763 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]764
765 sandbox_virtio1 {
766 compatible = "sandbox,virtio1";
767 };
768
769 sandbox_virtio2 {
770 compatible = "sandbox,virtio2";
771 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]772
773 pinctrl {
774 compatible = "sandbox,pinctrl";
775 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]776
777 hwspinlock@0 {
778 compatible = "sandbox,hwspinlock";
779 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]780
781 dma: dma {
782 compatible = "sandbox,dma";
783 #dma-cells = <1>;
784
785 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
786 dma-names = "m2m", "tx0", "rx0";
787 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]788};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]789
790#include "sandbox_pmic.dtsi"