Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 2 | /* |
3 | * (C) Copyright 2003 | ||||
4 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | ||||
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 5 | */ |
6 | |||||
7 | #include <common.h> | ||||
8 | #include <command.h> | ||||
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Daniel Schwierzeck | ed16050 | 2015-01-29 14:56:20 +0100 | [diff] [blame] | 10 | #include <linux/compiler.h> |
Paul Burton | dc2037e | 2016-09-21 11:18:48 +0100 | [diff] [blame] | 11 | #include <asm/cache.h> |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 12 | #include <asm/mipsregs.h> |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 13 | #include <asm/reboot.h> |
14 | |||||
developer | 80e446e | 2020-11-12 16:35:38 +0800 | [diff] [blame] | 15 | #if !CONFIG_IS_ENABLED(SYSRESET) |
Daniel Schwierzeck | ed16050 | 2015-01-29 14:56:20 +0100 | [diff] [blame] | 16 | void __weak _machine_restart(void) |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 17 | { |
18 | fprintf(stderr, "*** reset failed ***\n"); | ||||
19 | |||||
20 | while (1) | ||||
21 | /* NOP */; | ||||
22 | } | ||||
23 | |||||
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 24 | int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 25 | { |
26 | _machine_restart(); | ||||
27 | |||||
28 | return 0; | ||||
29 | } | ||||
Álvaro Fernández Rojas | 2ec1f98 | 2017-04-25 00:39:15 +0200 | [diff] [blame] | 30 | #endif |
Zhi-zhou Zhang | e0d6df5 | 2012-10-16 15:02:08 +0200 | [diff] [blame] | 31 | |
Paul Burton | dc2037e | 2016-09-21 11:18:48 +0100 | [diff] [blame] | 32 | int arch_cpu_init(void) |
33 | { | ||||
34 | mips_cache_probe(); | ||||
35 | return 0; | ||||
36 | } |