blob: a859a5b26a4eef2361add566f7bfe1c0c0f30ebe [file] [log] [blame]
developerd48dd9a2018-12-20 16:12:51 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 */
5
6#ifndef _DT_BINDINGS_MTK_RESET_H_
7#define _DT_BINDINGS_MTK_RESET_H_
8
developercc0b4c02019-08-22 12:26:52 +02009/* ETHSYS resets */
developerd48dd9a2018-12-20 16:12:51 +080010#define ETHSYS_PPE_RST 31
developerd48dd9a2018-12-20 16:12:51 +080011#define ETHSYS_GMAC_RST 23
developerd48dd9a2018-12-20 16:12:51 +080012#define ETHSYS_FE_RST 6
13#define ETHSYS_MCM_RST 2
14#define ETHSYS_SYS_RST 0
15
developera3d81fe2019-07-29 22:17:47 +080016/* HIFSYS resets */
17#define HIFSYS_PCIE2_RST 26
18#define HIFSYS_PCIE1_RST 25
19#define HIFSYS_PCIE0_RST 24
20#define HIFSYS_UPHY1_RST 22
21#define HIFSYS_UPHY0_RST 21
22#define HIFSYS_UHOST1_RST 4
23#define HIFSYS_UHOST0_RST 3
24
developerd48dd9a2018-12-20 16:12:51 +080025#endif /* _DT_BINDINGS_MTK_RESET_H_ */