Michal Simek | e34f1f6 | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 1 | menu "FPGA support" |
| 2 | |
Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 3 | config FPGA |
| 4 | bool |
| 5 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 6 | config FPGA_ALTERA |
| 7 | bool "Enable Altera FPGA drivers" |
| 8 | select FPGA |
| 9 | help |
| 10 | Say Y here to enable the Altera FPGA driver |
| 11 | |
| 12 | This provides basic infrastructure to support Altera FPGA devices. |
| 13 | Enable Altera FPGA specific functions which includes bitstream |
| 14 | (in BIT format), fpga and device validation. |
| 15 | |
Tien Fong Chee | cde4219 | 2017-07-26 13:05:40 +0800 | [diff] [blame] | 16 | config FPGA_SOCFPGA |
| 17 | bool "Enable Gen5 and Arria10 common FPGA drivers" |
| 18 | select FPGA_ALTERA |
| 19 | help |
| 20 | Say Y here to enable the Gen5 and Arria10 common FPGA driver |
| 21 | |
| 22 | This provides common functionality for Gen5 and Arria10 devices. |
| 23 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 24 | config FPGA_CYCLON2 |
| 25 | bool "Enable Altera FPGA driver for Cyclone II" |
| 26 | depends on FPGA_ALTERA |
| 27 | help |
| 28 | Say Y here to enable the Altera Cyclone II FPGA specific driver |
| 29 | |
| 30 | This provides common functionality for Altera Cyclone II devices. |
| 31 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 32 | on Altera Cyclone II device. |
| 33 | |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 34 | config FPGA_INTEL_SDM_MAILBOX |
| 35 | bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" |
Chee Hong Ang | 89ac34d | 2020-08-07 11:50:05 +0800 | [diff] [blame] | 36 | depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 37 | select FPGA_ALTERA |
| 38 | help |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 39 | Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 40 | |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 41 | This provides common functionality for Intel FPGA devices. |
| 42 | Enable FPGA driver for writing full bitstream into Intel FPGA |
| 43 | devices through SDM (Secure Device Manager) Mailbox. |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 44 | |
Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 45 | config FPGA_XILINX |
| 46 | bool "Enable Xilinx FPGA drivers" |
| 47 | select FPGA |
| 48 | help |
| 49 | Enable Xilinx FPGA specific functions which includes bitstream |
| 50 | (in BIT format), fpga and device validation. |
| 51 | |
| 52 | config FPGA_ZYNQMPPL |
| 53 | bool "Enable Xilinx FPGA driver for ZynqMP" |
| 54 | depends on FPGA_XILINX |
| 55 | help |
| 56 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 57 | on Xilinx Zynq UltraScale+ (ZynqMP) device. |
| 58 | |
Siva Durga Prasad Paladugu | b739897 | 2019-08-05 15:54:59 +0530 | [diff] [blame] | 59 | config FPGA_VERSALPL |
| 60 | bool "Enable Xilinx FPGA driver for Versal" |
| 61 | depends on FPGA_XILINX |
| 62 | help |
| 63 | Enable FPGA driver for loading bitstream in PDI format on Xilinx |
| 64 | Versal device. PDI is a new programmable device image format for |
| 65 | Versal. The bitstream will only be generated as PDI for Versal |
| 66 | platform. |
| 67 | |
Vipul Kumar | b8f64b9 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 68 | config FPGA_SPARTAN3 |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 69 | bool "Enable Spartan3 FPGA driver" |
Robert Hancock | be7f746 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 70 | depends on FPGA_XILINX |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 71 | help |
| 72 | Enable Spartan3 FPGA driver for loading in BIT format. |
Vipul Kumar | b8f64b9 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 73 | |
Robert Hancock | be7f746 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 74 | config FPGA_VIRTEX2 |
| 75 | bool "Enable Xilinx Virtex-II and later FPGA driver" |
| 76 | depends on FPGA_XILINX |
| 77 | help |
| 78 | Enable Virtex-II FPGA driver for loading in BIT format. This driver |
| 79 | also supports many newer Xilinx FPGA families. |
| 80 | |
Vipul Kumar | 4a4946b | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 81 | config FPGA_ZYNQPL |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 82 | bool "Enable Xilinx FPGA for Zynq" |
| 83 | depends on ARCH_ZYNQ |
| 84 | help |
| 85 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 86 | on Xilinx Zynq devices. |
Vipul Kumar | 4a4946b | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 87 | |
Michal Simek | e34f1f6 | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 88 | endmenu |