blob: 9aa0a9b05233761afe20793c3007b13ee8b187c8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan66cba6b2015-03-20 17:08:54 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 *
5 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
Chunhe Lan66cba6b2015-03-20 17:08:54 +08006 */
7
8#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07009#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -070010#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060011#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -070012#include <init.h>
Chunhe Lan66cba6b2015-03-20 17:08:54 +080013#include <asm/spl.h>
14#include <malloc.h>
15#include <ns16550.h>
16#include <nand.h>
17#include <mmc.h>
18#include <fsl_esdhc.h>
19#include <i2c.h>
20
21#include "t4rdb.h"
22
23#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
24
25DECLARE_GLOBAL_DATA_PTR;
26
27phys_size_t get_effective_memsize(void)
28{
29 return CONFIG_SYS_L3_SIZE;
30}
31
32unsigned long get_board_sys_clk(void)
33{
34 return CONFIG_SYS_CLK_FREQ;
35}
36
37unsigned long get_board_ddr_clk(void)
38{
39 return CONFIG_DDR_CLK_FREQ;
40}
41
42void board_init_f(ulong bootflag)
43{
44 u32 plat_ratio, sys_clk, ccb_clk;
45 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
46
47 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
48 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
49
50 /* Update GD pointer */
51 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
52
53 /* compiler optimization barrier needed for GCC >= 3.4 */
54 __asm__ __volatile__("" : : : "memory");
55
56 console_init_f();
57
58 /* initialize selected port with appropriate baud rate */
59 sys_clk = get_board_sys_clk();
60 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
61 ccb_clk = sys_clk * plat_ratio / 2;
62
63 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
64 ccb_clk / 16 / CONFIG_BAUDRATE);
65
66 puts("\nSD boot...\n");
67
68 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
69}
70
71void board_init_r(gd_t *gd, ulong dest_addr)
72{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090073 struct bd_info *bd;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080074
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090075 bd = (struct bd_info *)(gd + sizeof(gd_t));
76 memset(bd, 0, sizeof(struct bd_info));
Chunhe Lan66cba6b2015-03-20 17:08:54 +080077 gd->bd = bd;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080078
Simon Glass302445a2017-01-23 13:31:22 -070079 arch_cpu_init();
Chunhe Lan66cba6b2015-03-20 17:08:54 +080080 get_clocks();
81 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
82 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040083 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080084
85 mmc_initialize(bd);
86 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050087 (uchar *)SPL_ENV_ADDR);
Chunhe Lan66cba6b2015-03-20 17:08:54 +080088
Tom Rini5cd7ece2019-11-18 20:02:10 -050089 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -060090 gd->env_valid = ENV_VALID;
Chunhe Lan66cba6b2015-03-20 17:08:54 +080091
92 i2c_init_all();
93
Simon Glassd35f3382017-04-06 12:47:05 -060094 dram_init();
Chunhe Lan66cba6b2015-03-20 17:08:54 +080095
96 mmc_boot();
97}