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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08002/* Copyright 2013 Freescale Semiconductor, Inc.
Shengzhou Liu11ff48a2014-04-18 16:43:40 +08003 */
4
5#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07006#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -07009#include <init.h>
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080010#include <malloc.h>
11#include <ns16550.h>
12#include <nand.h>
13#include <i2c.h>
14#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <spi_flash.h>
Simon Glassdd8e2242016-09-24 18:20:10 -060017#include "../common/spl.h"
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080018
19DECLARE_GLOBAL_DATA_PTR;
20
21phys_size_t get_effective_memsize(void)
22{
23 return CONFIG_SYS_L3_SIZE;
24}
25
26unsigned long get_board_sys_clk(void)
27{
28 return CONFIG_SYS_CLK_FREQ;
29}
30
31unsigned long get_board_ddr_clk(void)
32{
33 return CONFIG_DDR_CLK_FREQ;
34}
35
36void board_init_f(ulong bootflag)
37{
38 u32 plat_ratio, sys_clk, ccb_clk;
39 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
40
41 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
42 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
43
44 /* Update GD pointer */
45 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
46
47 console_init_f();
48
49 /* initialize selected port with appropriate baud rate */
50 sys_clk = get_board_sys_clk();
51 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
52 ccb_clk = sys_clk * plat_ratio / 2;
53
54 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
55 ccb_clk / 16 / CONFIG_BAUDRATE);
56
57#if defined(CONFIG_SPL_MMC_BOOT)
58 puts("\nSD boot...\n");
59#elif defined(CONFIG_SPL_SPI_BOOT)
60 puts("\nSPI boot...\n");
61#elif defined(CONFIG_SPL_NAND_BOOT)
62 puts("\nNAND boot...\n");
63#endif
64
65 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
66}
67
68void board_init_r(gd_t *gd, ulong dest_addr)
69{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090070 struct bd_info *bd;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080071
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090072 bd = (struct bd_info *)(gd + sizeof(gd_t));
73 memset(bd, 0, sizeof(struct bd_info));
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080074 gd->bd = bd;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080075
Simon Glass302445a2017-01-23 13:31:22 -070076 arch_cpu_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080077 get_clocks();
78 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
79 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040080 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080081
82#ifdef CONFIG_SPL_NAND_BOOT
83 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050084 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080085#endif
86#ifdef CONFIG_SPL_MMC_BOOT
87 mmc_initialize(bd);
88 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050089 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080090#endif
91#ifdef CONFIG_SPL_SPI_BOOT
Simon Glassdd8e2242016-09-24 18:20:10 -060092 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -050093 (uchar *)SPL_ENV_ADDR);
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080094#endif
95
Tom Rini5cd7ece2019-11-18 20:02:10 -050096 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -060097 gd->env_valid = ENV_VALID;
Shengzhou Liu11ff48a2014-04-18 16:43:40 +080098
99 i2c_init_all();
100
Simon Glassd35f3382017-04-06 12:47:05 -0600101 dram_init();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +0800102
103#ifdef CONFIG_SPL_MMC_BOOT
104 mmc_boot();
105#elif defined(CONFIG_SPL_SPI_BOOT)
Simon Glassdd8e2242016-09-24 18:20:10 -0600106 fsl_spi_boot();
Shengzhou Liu11ff48a2014-04-18 16:43:40 +0800107#elif defined(CONFIG_SPL_NAND_BOOT)
108 nand_boot();
109#endif
110}