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Siva Durga Prasad Paladugu5a7fdb82019-01-08 21:47:29 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal Mini eMMC1 Configuration
4 *
5 * (C) Copyright 2018-2019, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13/ {
14 compatible = "xlnx,versal";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 model = "Xilinx Versal MINI eMMC1";
18
19 clk25: clk25 {
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
22 clock-frequency = <25000000>;
23 };
24
25 dcc: dcc {
26 compatible = "arm,dcc";
27 status = "okay";
28 u-boot,dm-pre-reloc;
29 };
30
31 amba: amba {
32 u-boot,dm-pre-reloc;
33 compatible = "simple-bus";
34 #address-cells = <0x2>;
35 #size-cells = <0x2>;
36 ranges;
37
Michal Simek1e3cc7e2019-10-01 15:52:35 +020038 sdhci1: sdhci@f1050000 {
Siva Durga Prasad Paladugu5a7fdb82019-01-08 21:47:29 +053039 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
40 status = "okay";
41 reg = <0x0 0xf1050000 0x0 0x10000>;
42 clock-names = "clk_xin", "clk_ahb";
43 clocks = <&clk25 &clk25>;
44 xlnx,device_id = <1>;
45 no-1-8-v;
Michal Simek3b662642020-07-22 17:42:43 +020046 xlnx,mio-bank = <0>;
Siva Durga Prasad Paladugu5a7fdb82019-01-08 21:47:29 +053047 #stream-id-cells = <1>;
48 };
49 };
50
51 aliases {
52 serial0 = &dcc;
53 mmc0 = &sdhci1;
54 };
55
56 chosen {
57 stdout-path = "serial0:115200";
58 };
59
60 memory@0 {
61 device_type = "memory";
62 reg = <0x0 0x0 0x0 0x20000000>;
63 };
64};