| Svyatoslav Ryhel | f4ec2e6 | 2024-08-01 19:11:17 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * T30 Grouper SPL stage configuration |
| 4 | * |
| 5 | * (C) Copyright 2010-2013 |
| 6 | * NVIDIA Corporation <www.nvidia.com> |
| 7 | * |
| 8 | * (C) Copyright 2022 |
| 9 | * Svyatoslav Ryhel <clamor95@gmail.com> |
| 10 | */ |
| 11 | |
| 12 | #include <asm/gpio.h> |
| 13 | #include <asm/arch/pinmux.h> |
| 14 | #include <asm/arch/tegra.h> |
| 15 | #include <asm/arch-tegra/tegra_i2c.h> |
| 16 | #include <spl_gpio.h> |
| 17 | #include <linux/delay.h> |
| 18 | |
| 19 | #define MAX77663_I2C_ADDR (0x3C << 1) |
| 20 | |
| 21 | #define MAX77663_REG_SD0 0x16 |
| 22 | #define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) |
| 23 | #define MAX77663_REG_SD1 0x17 |
| 24 | #define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) |
| 25 | #define MAX77663_REG_LDO4 0x2B |
| 26 | #define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) |
| 27 | |
| 28 | #define MAX77663_REG_GPIO4 0x3A |
| 29 | #define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) |
| 30 | |
| 31 | #define TPS65911_I2C_ADDR (0x2D << 1) |
| 32 | |
| 33 | #define TPS65911_VDDCTRL_OP_REG 0x28 |
| 34 | #define TPS65911_VDDCTRL_SR_REG 0x27 |
| 35 | #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) |
| 36 | #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) |
| 37 | |
| 38 | #define TPS62361B_I2C_ADDR (0x60 << 1) |
| 39 | |
| 40 | #define TPS62361B_SET3_REG 0x03 |
| 41 | #define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) |
| 42 | |
| 43 | /* |
| 44 | * PCB_ID[8] is GMI_CS2_N_PK3 |
| 45 | * |
| 46 | * PMIC module detection |
| 47 | * ============================== |
| 48 | * PCB_ID[8] 0 1 |
| 49 | * PMIC Maxim TI |
| 50 | */ |
| 51 | static bool ti_pmic_detected(void) |
| 52 | { |
| 53 | /* Configure pinmux */ |
| 54 | pinmux_set_func(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_FUNC_GMI); |
| 55 | pinmux_set_pullupdown(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PULL_DOWN); |
| 56 | pinmux_tristate_enable(PMUX_PINGRP_GMI_CS2_N_PK3); |
| 57 | pinmux_set_io(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PIN_INPUT); |
| 58 | |
| 59 | spl_gpio_input(NULL, TEGRA_GPIO(K, 3)); |
| 60 | return spl_gpio_get_value(NULL, TEGRA_GPIO(K, 3)); |
| 61 | } |
| 62 | |
| 63 | static void max_enable_cpu_vdd(void) |
| 64 | { |
| 65 | /* Set VDD_CORE to 1.200V. */ |
| 66 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); |
| 67 | |
| 68 | udelay(1000); |
| 69 | |
| 70 | /* Bring up VDD_CPU to 1.0125V. */ |
| 71 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); |
| 72 | udelay(1000); |
| 73 | |
| 74 | /* Bring up VDD_RTC to 1.200V. */ |
| 75 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); |
| 76 | udelay(10 * 1000); |
| 77 | |
| 78 | /* Set 32k-out gpio state */ |
| 79 | tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); |
| 80 | } |
| 81 | |
| 82 | static void ti_enable_cpu_vdd(void) |
| 83 | { |
| 84 | /* Set VDD_CORE to 1.200V. */ |
| 85 | tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); |
| 86 | |
| 87 | udelay(1000); |
| 88 | |
| 89 | /* |
| 90 | * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. |
| 91 | * First set VDD to 1.0125V, then enable the VDD regulator. |
| 92 | */ |
| 93 | tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); |
| 94 | udelay(1000); |
| 95 | tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); |
| 96 | udelay(10 * 1000); |
| 97 | } |
| 98 | |
| 99 | void pmic_enable_cpu_vdd(void) |
| 100 | { |
| 101 | if (ti_pmic_detected()) |
| 102 | ti_enable_cpu_vdd(); |
| 103 | else |
| 104 | max_enable_cpu_vdd(); |
| 105 | } |