Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Xilinx, Inc. |
| 4 | * |
| 5 | * Xilinx Zynq NAND Flash Controller Driver |
| 6 | * This driver is based on plat_nand.c and mxc_nand.c drivers |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 11 | #include <malloc.h> |
| 12 | #include <asm/io.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 14 | #include <linux/errno.h> |
| 15 | #include <nand.h> |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 16 | #include <linux/ioport.h> |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 17 | #include <linux/mtd/mtd.h> |
Masahiro Yamada | 2b7a873 | 2017-11-30 13:45:24 +0900 | [diff] [blame] | 18 | #include <linux/mtd/rawnand.h> |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 19 | #include <linux/mtd/partitions.h> |
| 20 | #include <linux/mtd/nand_ecc.h> |
| 21 | #include <asm/arch/hardware.h> |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 22 | #include <asm/arch/sys_proto.h> |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 23 | #include <dm.h> |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 24 | |
| 25 | /* The NAND flash driver defines */ |
| 26 | #define ZYNQ_NAND_CMD_PHASE 1 |
| 27 | #define ZYNQ_NAND_DATA_PHASE 2 |
| 28 | #define ZYNQ_NAND_ECC_SIZE 512 |
| 29 | #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0) |
| 30 | #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0) |
| 31 | #define ZYNQ_NAND_ECC_STATUS (1 << 6) |
| 32 | #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4) |
| 33 | #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6) |
| 34 | #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4) |
| 35 | #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC |
| 36 | |
| 37 | /* Flash memory controller operating parameters */ |
| 38 | #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \ |
| 39 | (0x1 << 4) | /* Clear interrupt */ \ |
| 40 | (0x1 << 6)) /* Disable ECC interrupt */ |
| 41 | |
Jeff Westfahl | 313b9c3 | 2017-11-06 00:34:46 -0800 | [diff] [blame] | 42 | #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS |
| 43 | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 44 | /* Assuming 50MHz clock (20ns cycle time) and 3V operation */ |
| 45 | #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ |
| 46 | (0x2 << 17) | /* t_ar from nand_cycles */ \ |
| 47 | (0x1 << 14) | /* t_clr from nand_cycles */ \ |
| 48 | (0x3 << 11) | /* t_wp from nand_cycles */ \ |
| 49 | (0x2 << 8) | /* t_rea from nand_cycles */ \ |
| 50 | (0x5 << 4) | /* t_wc from nand_cycles */ \ |
| 51 | (0x5 << 0)) /* t_rc from nand_cycles */ |
Jeff Westfahl | 313b9c3 | 2017-11-06 00:34:46 -0800 | [diff] [blame] | 52 | #endif |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 53 | |
| 54 | |
| 55 | #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ |
| 56 | (0x2 << 21)) /* UpdateRegs operation */ |
| 57 | |
| 58 | #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \ |
| 59 | (0x1 << 4) | /* ECC read at end of page */ \ |
| 60 | (0x0 << 5)) /* No Jumping */ |
| 61 | |
| 62 | #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ |
| 63 | (0x00 << 8) | /* Read command */ \ |
| 64 | (0x30 << 16) | /* Read End command */ \ |
| 65 | (0x1 << 24)) /* Read End command calid */ |
| 66 | |
| 67 | #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ |
| 68 | (0x05 << 8) | /* Read col change cmd */ \ |
| 69 | (0xE0 << 16) | /* Read col change end cmd */ \ |
| 70 | (0x1 << 24)) /* Read col change |
| 71 | end cmd valid */ |
| 72 | /* AXI Address definitions */ |
| 73 | #define START_CMD_SHIFT 3 |
| 74 | #define END_CMD_SHIFT 11 |
| 75 | #define END_CMD_VALID_SHIFT 20 |
| 76 | #define ADDR_CYCLES_SHIFT 21 |
| 77 | #define CLEAR_CS_SHIFT 21 |
| 78 | #define ECC_LAST_SHIFT 10 |
| 79 | #define COMMAND_PHASE (0 << 19) |
| 80 | #define DATA_PHASE (1 << 19) |
| 81 | #define ONDIE_ECC_FEATURE_ADDR 0x90 |
| 82 | #define ONDIE_ECC_FEATURE_ENABLE 0x08 |
| 83 | |
| 84 | #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */ |
| 85 | #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */ |
| 86 | |
| 87 | /* ECC block registers bit position and bit mask */ |
| 88 | #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ |
| 89 | #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ |
| 90 | |
Siva Durga Prasad Paladugu | 2e60159 | 2017-05-25 12:15:24 +0530 | [diff] [blame] | 91 | #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F |
| 92 | #define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0 |
| 93 | |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 94 | #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 |
| 95 | #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 |
| 96 | |
| 97 | enum zynq_nand_bus_width { |
| 98 | NAND_BW_UNKNOWN = -1, |
| 99 | NAND_BW_8BIT, |
| 100 | NAND_BW_16BIT, |
| 101 | }; |
| 102 | |
Joe Hershberger | e7fa437 | 2017-11-06 18:16:10 -0800 | [diff] [blame] | 103 | #ifndef NAND_CMD_LOCK_TIGHT |
| 104 | #define NAND_CMD_LOCK_TIGHT 0x2c |
| 105 | #endif |
| 106 | |
| 107 | #ifndef NAND_CMD_LOCK_STATUS |
| 108 | #define NAND_CMD_LOCK_STATUS 0x7a |
| 109 | #endif |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 110 | |
| 111 | /* SMC register set */ |
| 112 | struct zynq_nand_smc_regs { |
| 113 | u32 csr; /* 0x00 */ |
| 114 | u32 reserved0[2]; |
| 115 | u32 cfr; /* 0x0C */ |
| 116 | u32 dcr; /* 0x10 */ |
| 117 | u32 scr; /* 0x14 */ |
| 118 | u32 sor; /* 0x18 */ |
| 119 | u32 reserved1[249]; |
| 120 | u32 esr; /* 0x400 */ |
| 121 | u32 emcr; /* 0x404 */ |
| 122 | u32 emcmd1r; /* 0x408 */ |
| 123 | u32 emcmd2r; /* 0x40C */ |
| 124 | u32 reserved2[2]; |
| 125 | u32 eval0r; /* 0x418 */ |
| 126 | }; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 127 | |
| 128 | /* |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 129 | * struct nand_config - Defines the NAND flash driver instance |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 130 | * @parts: Pointer to the mtd_partition structure |
| 131 | * @nand_base: Virtual address of the NAND flash device |
| 132 | * @end_cmd_pending: End command is pending |
| 133 | * @end_cmd: End command |
| 134 | */ |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 135 | struct nand_config { |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 136 | void __iomem *nand_base; |
| 137 | u8 end_cmd_pending; |
| 138 | u8 end_cmd; |
| 139 | }; |
| 140 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 141 | struct nand_drv { |
| 142 | struct zynq_nand_smc_regs *reg; |
| 143 | struct nand_config config; |
| 144 | }; |
| 145 | |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 146 | struct zynq_nand_info { |
| 147 | struct udevice *dev; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 148 | struct nand_drv nand_ctrl; |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 149 | struct nand_chip nand_chip; |
| 150 | }; |
| 151 | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 152 | /* |
| 153 | * struct zynq_nand_command_format - Defines NAND flash command format |
| 154 | * @start_cmd: First cycle command (Start command) |
| 155 | * @end_cmd: Second cycle command (Last command) |
| 156 | * @addr_cycles: Number of address cycles required to send the address |
| 157 | * @end_cmd_valid: The second cycle command is valid for cmd or data phase |
| 158 | */ |
| 159 | struct zynq_nand_command_format { |
| 160 | u8 start_cmd; |
| 161 | u8 end_cmd; |
| 162 | u8 addr_cycles; |
| 163 | u8 end_cmd_valid; |
| 164 | }; |
| 165 | |
| 166 | /* The NAND flash operations command format */ |
| 167 | static const struct zynq_nand_command_format zynq_nand_commands[] = { |
| 168 | {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE}, |
| 169 | {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE}, |
| 170 | {NAND_CMD_READID, NAND_CMD_NONE, 1, 0}, |
| 171 | {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0}, |
| 172 | {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE}, |
| 173 | {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0}, |
| 174 | {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE}, |
| 175 | {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0}, |
| 176 | {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0}, |
| 177 | {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0}, |
| 178 | {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0}, |
Joe Hershberger | e7fa437 | 2017-11-06 18:16:10 -0800 | [diff] [blame] | 179 | {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0}, |
| 180 | {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0}, |
| 181 | {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0}, |
| 182 | {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0}, |
| 183 | {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0}, |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 184 | {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, |
| 185 | /* Add all the flash commands supported by the flash device */ |
| 186 | }; |
| 187 | |
| 188 | /* Define default oob placement schemes for large and small page devices */ |
| 189 | static struct nand_ecclayout nand_oob_16 = { |
| 190 | .eccbytes = 3, |
| 191 | .eccpos = {0, 1, 2}, |
| 192 | .oobfree = { |
| 193 | { .offset = 8, .length = 8 } |
| 194 | } |
| 195 | }; |
| 196 | |
| 197 | static struct nand_ecclayout nand_oob_64 = { |
| 198 | .eccbytes = 12, |
| 199 | .eccpos = { |
| 200 | 52, 53, 54, 55, 56, 57, |
| 201 | 58, 59, 60, 61, 62, 63}, |
| 202 | .oobfree = { |
| 203 | { .offset = 2, .length = 50 } |
| 204 | } |
| 205 | }; |
| 206 | |
| 207 | static struct nand_ecclayout ondie_nand_oob_64 = { |
| 208 | .eccbytes = 32, |
| 209 | |
| 210 | .eccpos = { |
| 211 | 8, 9, 10, 11, 12, 13, 14, 15, |
| 212 | 24, 25, 26, 27, 28, 29, 30, 31, |
| 213 | 40, 41, 42, 43, 44, 45, 46, 47, |
| 214 | 56, 57, 58, 59, 60, 61, 62, 63 |
| 215 | }, |
| 216 | |
| 217 | .oobfree = { |
| 218 | { .offset = 4, .length = 4 }, |
| 219 | { .offset = 20, .length = 4 }, |
| 220 | { .offset = 36, .length = 4 }, |
| 221 | { .offset = 52, .length = 4 } |
| 222 | } |
| 223 | }; |
| 224 | |
| 225 | /* bbt decriptors for chips with on-die ECC and |
| 226 | chips with 64-byte OOB */ |
| 227 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; |
| 228 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; |
| 229 | |
| 230 | static struct nand_bbt_descr bbt_main_descr = { |
| 231 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
| 232 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 233 | .offs = 4, |
| 234 | .len = 4, |
| 235 | .veroffs = 20, |
| 236 | .maxblocks = 4, |
| 237 | .pattern = bbt_pattern |
| 238 | }; |
| 239 | |
| 240 | static struct nand_bbt_descr bbt_mirror_descr = { |
| 241 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
| 242 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 243 | .offs = 4, |
| 244 | .len = 4, |
| 245 | .veroffs = 20, |
| 246 | .maxblocks = 4, |
| 247 | .pattern = mirror_pattern |
| 248 | }; |
| 249 | |
| 250 | /* |
| 251 | * zynq_nand_waitfor_ecc_completion - Wait for ECC completion |
| 252 | * |
| 253 | * returns: status for command completion, -1 for Timeout |
| 254 | */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 255 | static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd) |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 256 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 257 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
| 258 | struct nand_drv *smc = nand_get_controller_data(nand_chip); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 259 | unsigned long timeout; |
| 260 | u32 status; |
| 261 | |
| 262 | /* Wait max 10us */ |
| 263 | timeout = 10; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 264 | status = readl(&smc->reg->esr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 265 | while (status & ZYNQ_NAND_ECC_BUSY) { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 266 | status = readl(&smc->reg->esr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 267 | if (timeout == 0) |
| 268 | return -1; |
| 269 | timeout--; |
| 270 | udelay(1); |
| 271 | } |
| 272 | |
| 273 | return status; |
| 274 | } |
| 275 | |
| 276 | /* |
| 277 | * zynq_nand_init_nand_flash - Initialize NAND controller |
| 278 | * @option: Device property flags |
| 279 | * |
| 280 | * This function initializes the NAND flash interface on the NAND controller. |
| 281 | * |
| 282 | * returns: 0 on success or error value on failure |
| 283 | */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 284 | static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option) |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 285 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 286 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
| 287 | struct nand_drv *smc = nand_get_controller_data(nand_chip); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 288 | u32 status; |
| 289 | |
| 290 | /* disable interrupts */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 291 | writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr); |
Jeff Westfahl | 313b9c3 | 2017-11-06 00:34:46 -0800 | [diff] [blame] | 292 | #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 293 | /* Initialize the NAND interface by setting cycles and operation mode */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 294 | writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr); |
Jeff Westfahl | 313b9c3 | 2017-11-06 00:34:46 -0800 | [diff] [blame] | 295 | #endif |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 296 | if (option & NAND_BUSWIDTH_16) |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 297 | writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 298 | else |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 299 | writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 300 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 301 | writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 302 | |
| 303 | /* Wait till the ECC operation is complete */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 304 | status = zynq_nand_waitfor_ecc_completion(mtd); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 305 | if (status < 0) { |
| 306 | printf("%s: Timeout\n", __func__); |
| 307 | return status; |
| 308 | } |
| 309 | |
| 310 | /* Set the command1 and command2 register */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 311 | writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r); |
| 312 | writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 313 | |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | /* |
| 318 | * zynq_nand_calculate_hwecc - Calculate Hardware ECC |
| 319 | * @mtd: Pointer to the mtd_info structure |
| 320 | * @data: Pointer to the page data |
| 321 | * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored |
| 322 | * |
| 323 | * This function retrieves the Hardware ECC data from the controller and returns |
| 324 | * ECC data back to the MTD subsystem. |
| 325 | * |
| 326 | * returns: 0 on success or error value on failure |
| 327 | */ |
| 328 | static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, |
| 329 | u8 *ecc_code) |
| 330 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 331 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
| 332 | struct nand_drv *smc = nand_get_controller_data(nand_chip); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 333 | u32 ecc_value = 0; |
| 334 | u8 ecc_reg, ecc_byte; |
| 335 | u32 ecc_status; |
| 336 | |
| 337 | /* Wait till the ECC operation is complete */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 338 | ecc_status = zynq_nand_waitfor_ecc_completion(mtd); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 339 | if (ecc_status < 0) { |
| 340 | printf("%s: Timeout\n", __func__); |
| 341 | return ecc_status; |
| 342 | } |
| 343 | |
| 344 | for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { |
| 345 | /* Read ECC value for each block */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 346 | ecc_value = readl(&smc->reg->eval0r + ecc_reg); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 347 | |
| 348 | /* Get the ecc status from ecc read value */ |
| 349 | ecc_status = (ecc_value >> 24) & 0xFF; |
| 350 | |
| 351 | /* ECC value valid */ |
| 352 | if (ecc_status & ZYNQ_NAND_ECC_STATUS) { |
| 353 | for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) { |
| 354 | /* Copy ECC bytes to MTD buffer */ |
| 355 | *ecc_code = ecc_value & 0xFF; |
| 356 | ecc_value = ecc_value >> 8; |
| 357 | ecc_code++; |
| 358 | } |
| 359 | } else { |
| 360 | debug("%s: ecc status failed\n", __func__); |
| 361 | } |
| 362 | } |
| 363 | |
| 364 | return 0; |
| 365 | } |
| 366 | |
| 367 | /* |
| 368 | * onehot - onehot function |
| 369 | * @value: value to check for onehot |
| 370 | * |
| 371 | * This function checks whether a value is onehot or not. |
| 372 | * onehot is if and only if one bit is set. |
| 373 | * |
| 374 | * FIXME: Try to move this in common.h |
| 375 | */ |
| 376 | static bool onehot(unsigned short value) |
| 377 | { |
| 378 | bool onehot; |
| 379 | |
| 380 | onehot = value && !(value & (value - 1)); |
| 381 | return onehot; |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * zynq_nand_correct_data - ECC correction function |
| 386 | * @mtd: Pointer to the mtd_info structure |
| 387 | * @buf: Pointer to the page data |
| 388 | * @read_ecc: Pointer to the ECC value read from spare data area |
| 389 | * @calc_ecc: Pointer to the calculated ECC value |
| 390 | * |
| 391 | * This function corrects the ECC single bit errors & detects 2-bit errors. |
| 392 | * |
| 393 | * returns: 0 if no ECC errors found |
| 394 | * 1 if single bit error found and corrected. |
| 395 | * -1 if multiple ECC errors found. |
| 396 | */ |
| 397 | static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, |
| 398 | unsigned char *read_ecc, unsigned char *calc_ecc) |
| 399 | { |
| 400 | unsigned char bit_addr; |
| 401 | unsigned int byte_addr; |
| 402 | unsigned short ecc_odd, ecc_even; |
| 403 | unsigned short read_ecc_lower, read_ecc_upper; |
| 404 | unsigned short calc_ecc_lower, calc_ecc_upper; |
| 405 | |
| 406 | read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff; |
| 407 | read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff; |
| 408 | |
| 409 | calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff; |
| 410 | calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff; |
| 411 | |
| 412 | ecc_odd = read_ecc_lower ^ calc_ecc_lower; |
| 413 | ecc_even = read_ecc_upper ^ calc_ecc_upper; |
| 414 | |
| 415 | if ((ecc_odd == 0) && (ecc_even == 0)) |
| 416 | return 0; /* no error */ |
| 417 | |
| 418 | if (ecc_odd == (~ecc_even & 0xfff)) { |
| 419 | /* bits [11:3] of error code is byte offset */ |
| 420 | byte_addr = (ecc_odd >> 3) & 0x1ff; |
| 421 | /* bits [2:0] of error code is bit offset */ |
| 422 | bit_addr = ecc_odd & 0x7; |
| 423 | /* Toggling error bit */ |
| 424 | buf[byte_addr] ^= (1 << bit_addr); |
| 425 | return 1; |
| 426 | } |
| 427 | |
| 428 | if (onehot(ecc_odd | ecc_even)) |
| 429 | return 1; /* one error in parity */ |
| 430 | |
| 431 | return -1; /* Uncorrectable error */ |
| 432 | } |
| 433 | |
| 434 | /* |
| 435 | * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function |
| 436 | * @mtd: mtd info structure |
| 437 | * @chip: nand chip info structure |
| 438 | * @page: page number to read |
| 439 | * @sndcmd: flag whether to issue read command or not |
| 440 | */ |
| 441 | static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
| 442 | int page) |
| 443 | { |
| 444 | unsigned long data_phase_addr = 0; |
| 445 | int data_width = 4; |
| 446 | u8 *p; |
| 447 | |
| 448 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
| 449 | |
| 450 | p = chip->oob_poi; |
| 451 | chip->read_buf(mtd, p, (mtd->oobsize - data_width)); |
| 452 | p += mtd->oobsize - data_width; |
| 453 | |
| 454 | data_phase_addr = (unsigned long)chip->IO_ADDR_R; |
| 455 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 456 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 457 | chip->read_buf(mtd, p, data_width); |
| 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | /* |
| 463 | * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function |
| 464 | * @mtd: mtd info structure |
| 465 | * @chip: nand chip info structure |
| 466 | * @page: page number to write |
| 467 | */ |
| 468 | static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
| 469 | int page) |
| 470 | { |
| 471 | int status = 0, data_width = 4; |
| 472 | const u8 *buf = chip->oob_poi; |
| 473 | unsigned long data_phase_addr = 0; |
| 474 | |
| 475 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
| 476 | |
| 477 | chip->write_buf(mtd, buf, (mtd->oobsize - data_width)); |
| 478 | buf += mtd->oobsize - data_width; |
| 479 | |
| 480 | data_phase_addr = (unsigned long)chip->IO_ADDR_W; |
| 481 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 482 | data_phase_addr |= (1 << END_CMD_VALID_SHIFT); |
| 483 | chip->IO_ADDR_W = (void __iomem *)data_phase_addr; |
| 484 | chip->write_buf(mtd, buf, data_width); |
| 485 | |
| 486 | /* Send command to program the OOB data */ |
| 487 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
| 488 | status = chip->waitfunc(mtd, chip); |
| 489 | |
| 490 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
| 491 | } |
| 492 | |
| 493 | /* |
| 494 | * zynq_nand_read_page_raw - [Intern] read raw page data without ecc |
| 495 | * @mtd: mtd info structure |
| 496 | * @chip: nand chip info structure |
| 497 | * @buf: buffer to store read data |
| 498 | * @oob_required: must write chip->oob_poi to OOB |
| 499 | * @page: page number to read |
| 500 | */ |
| 501 | static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 502 | u8 *buf, int oob_required, int page) |
| 503 | { |
| 504 | unsigned long data_width = 4; |
| 505 | unsigned long data_phase_addr = 0; |
| 506 | u8 *p; |
| 507 | |
| 508 | chip->read_buf(mtd, buf, mtd->writesize); |
| 509 | |
| 510 | p = chip->oob_poi; |
| 511 | chip->read_buf(mtd, p, (mtd->oobsize - data_width)); |
| 512 | p += (mtd->oobsize - data_width); |
| 513 | |
| 514 | data_phase_addr = (unsigned long)chip->IO_ADDR_R; |
| 515 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 516 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 517 | |
| 518 | chip->read_buf(mtd, p, data_width); |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd, |
| 523 | struct nand_chip *chip, u8 *buf, int oob_required, int page) |
| 524 | { |
| 525 | chip->read_buf(mtd, buf, mtd->writesize); |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | static int zynq_nand_read_subpage_raw(struct mtd_info *mtd, |
| 530 | struct nand_chip *chip, u32 data_offs, |
| 531 | u32 readlen, u8 *buf, int page) |
| 532 | { |
| 533 | if (data_offs != 0) { |
| 534 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1); |
| 535 | buf += data_offs; |
| 536 | } |
| 537 | chip->read_buf(mtd, buf, readlen); |
| 538 | |
| 539 | return 0; |
| 540 | } |
| 541 | |
| 542 | /* |
| 543 | * zynq_nand_write_page_raw - [Intern] raw page write function |
| 544 | * @mtd: mtd info structure |
| 545 | * @chip: nand chip info structure |
| 546 | * @buf: data buffer |
| 547 | * @oob_required: must write chip->oob_poi to OOB |
| 548 | */ |
| 549 | static int zynq_nand_write_page_raw(struct mtd_info *mtd, |
| 550 | struct nand_chip *chip, const u8 *buf, int oob_required, int page) |
| 551 | { |
| 552 | unsigned long data_width = 4; |
| 553 | unsigned long data_phase_addr = 0; |
| 554 | u8 *p; |
| 555 | |
| 556 | chip->write_buf(mtd, buf, mtd->writesize); |
| 557 | |
| 558 | p = chip->oob_poi; |
| 559 | chip->write_buf(mtd, p, (mtd->oobsize - data_width)); |
| 560 | p += (mtd->oobsize - data_width); |
| 561 | |
| 562 | data_phase_addr = (unsigned long)chip->IO_ADDR_W; |
| 563 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 564 | data_phase_addr |= (1 << END_CMD_VALID_SHIFT); |
| 565 | chip->IO_ADDR_W = (void __iomem *)data_phase_addr; |
| 566 | |
| 567 | chip->write_buf(mtd, p, data_width); |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | /* |
| 573 | * nand_write_page_hwecc - Hardware ECC based page write function |
| 574 | * @mtd: Pointer to the mtd info structure |
| 575 | * @chip: Pointer to the NAND chip info structure |
| 576 | * @buf: Pointer to the data buffer |
| 577 | * @oob_required: must write chip->oob_poi to OOB |
| 578 | * |
| 579 | * This functions writes data and hardware generated ECC values in to the page. |
| 580 | */ |
| 581 | static int zynq_nand_write_page_hwecc(struct mtd_info *mtd, |
| 582 | struct nand_chip *chip, const u8 *buf, int oob_required, int page) |
| 583 | { |
| 584 | int i, eccsteps, eccsize = chip->ecc.size; |
| 585 | u8 *ecc_calc = chip->buffers->ecccalc; |
| 586 | const u8 *p = buf; |
| 587 | u32 *eccpos = chip->ecc.layout->eccpos; |
| 588 | unsigned long data_phase_addr = 0; |
| 589 | unsigned long data_width = 4; |
| 590 | u8 *oob_ptr; |
| 591 | |
| 592 | for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { |
| 593 | chip->write_buf(mtd, p, eccsize); |
| 594 | p += eccsize; |
| 595 | } |
| 596 | chip->write_buf(mtd, p, (eccsize - data_width)); |
| 597 | p += eccsize - data_width; |
| 598 | |
| 599 | /* Set ECC Last bit to 1 */ |
| 600 | data_phase_addr = (unsigned long) chip->IO_ADDR_W; |
| 601 | data_phase_addr |= ZYNQ_NAND_ECC_LAST; |
| 602 | chip->IO_ADDR_W = (void __iomem *)data_phase_addr; |
| 603 | chip->write_buf(mtd, p, data_width); |
| 604 | |
| 605 | /* Wait for ECC to be calculated and read the error values */ |
| 606 | p = buf; |
| 607 | chip->ecc.calculate(mtd, p, &ecc_calc[0]); |
| 608 | |
| 609 | for (i = 0; i < chip->ecc.total; i++) |
| 610 | chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]); |
| 611 | |
| 612 | /* Clear ECC last bit */ |
| 613 | data_phase_addr = (unsigned long)chip->IO_ADDR_W; |
| 614 | data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; |
| 615 | chip->IO_ADDR_W = (void __iomem *)data_phase_addr; |
| 616 | |
| 617 | /* Write the spare area with ECC bytes */ |
| 618 | oob_ptr = chip->oob_poi; |
| 619 | chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); |
| 620 | |
| 621 | data_phase_addr = (unsigned long)chip->IO_ADDR_W; |
| 622 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 623 | data_phase_addr |= (1 << END_CMD_VALID_SHIFT); |
| 624 | chip->IO_ADDR_W = (void __iomem *)data_phase_addr; |
| 625 | oob_ptr += (mtd->oobsize - data_width); |
| 626 | chip->write_buf(mtd, oob_ptr, data_width); |
| 627 | |
| 628 | return 0; |
| 629 | } |
| 630 | |
| 631 | /* |
| 632 | * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page |
| 633 | * write function |
| 634 | * @mtd: mtd info structure |
| 635 | * @chip: nand chip info structure |
| 636 | * @buf: data buffer |
| 637 | * @oob_required: must write chip->oob_poi to OOB |
| 638 | */ |
| 639 | static int zynq_nand_write_page_swecc(struct mtd_info *mtd, |
| 640 | struct nand_chip *chip, const u8 *buf, int oob_required, int page) |
| 641 | { |
| 642 | int i, eccsize = chip->ecc.size; |
| 643 | int eccbytes = chip->ecc.bytes; |
| 644 | int eccsteps = chip->ecc.steps; |
| 645 | u8 *ecc_calc = chip->buffers->ecccalc; |
| 646 | const u8 *p = buf; |
| 647 | u32 *eccpos = chip->ecc.layout->eccpos; |
| 648 | |
| 649 | /* Software ecc calculation */ |
| 650 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
| 651 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
| 652 | |
| 653 | for (i = 0; i < chip->ecc.total; i++) |
| 654 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; |
| 655 | |
| 656 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
| 657 | } |
| 658 | |
| 659 | /* |
| 660 | * nand_read_page_hwecc - Hardware ECC based page read function |
| 661 | * @mtd: Pointer to the mtd info structure |
| 662 | * @chip: Pointer to the NAND chip info structure |
| 663 | * @buf: Pointer to the buffer to store read data |
| 664 | * @oob_required: must write chip->oob_poi to OOB |
| 665 | * @page: page number to read |
| 666 | * |
| 667 | * This functions reads data and checks the data integrity by comparing hardware |
| 668 | * generated ECC values and read ECC values from spare area. |
| 669 | * |
| 670 | * returns: 0 always and updates ECC operation status in to MTD structure |
| 671 | */ |
| 672 | static int zynq_nand_read_page_hwecc(struct mtd_info *mtd, |
| 673 | struct nand_chip *chip, u8 *buf, int oob_required, int page) |
| 674 | { |
| 675 | int i, stat, eccsteps, eccsize = chip->ecc.size; |
| 676 | int eccbytes = chip->ecc.bytes; |
| 677 | u8 *p = buf; |
| 678 | u8 *ecc_calc = chip->buffers->ecccalc; |
| 679 | u8 *ecc_code = chip->buffers->ecccode; |
| 680 | u32 *eccpos = chip->ecc.layout->eccpos; |
| 681 | unsigned long data_phase_addr = 0; |
| 682 | unsigned long data_width = 4; |
| 683 | u8 *oob_ptr; |
| 684 | |
| 685 | for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { |
| 686 | chip->read_buf(mtd, p, eccsize); |
| 687 | p += eccsize; |
| 688 | } |
| 689 | chip->read_buf(mtd, p, (eccsize - data_width)); |
| 690 | p += eccsize - data_width; |
| 691 | |
| 692 | /* Set ECC Last bit to 1 */ |
| 693 | data_phase_addr = (unsigned long)chip->IO_ADDR_R; |
| 694 | data_phase_addr |= ZYNQ_NAND_ECC_LAST; |
| 695 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 696 | chip->read_buf(mtd, p, data_width); |
| 697 | |
| 698 | /* Read the calculated ECC value */ |
| 699 | p = buf; |
| 700 | chip->ecc.calculate(mtd, p, &ecc_calc[0]); |
| 701 | |
| 702 | /* Clear ECC last bit */ |
| 703 | data_phase_addr = (unsigned long)chip->IO_ADDR_R; |
| 704 | data_phase_addr &= ~ZYNQ_NAND_ECC_LAST; |
| 705 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 706 | |
| 707 | /* Read the stored ECC value */ |
| 708 | oob_ptr = chip->oob_poi; |
| 709 | chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width)); |
| 710 | |
| 711 | /* de-assert chip select */ |
| 712 | data_phase_addr = (unsigned long)chip->IO_ADDR_R; |
| 713 | data_phase_addr |= ZYNQ_NAND_CLEAR_CS; |
| 714 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 715 | |
| 716 | oob_ptr += (mtd->oobsize - data_width); |
| 717 | chip->read_buf(mtd, oob_ptr, data_width); |
| 718 | |
| 719 | for (i = 0; i < chip->ecc.total; i++) |
| 720 | ecc_code[i] = ~(chip->oob_poi[eccpos[i]]); |
| 721 | |
| 722 | eccsteps = chip->ecc.steps; |
| 723 | p = buf; |
| 724 | |
| 725 | /* Check ECC error for all blocks and correct if it is correctable */ |
| 726 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
| 727 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
| 728 | if (stat < 0) |
| 729 | mtd->ecc_stats.failed++; |
| 730 | else |
| 731 | mtd->ecc_stats.corrected += stat; |
| 732 | } |
| 733 | return 0; |
| 734 | } |
| 735 | |
| 736 | /* |
| 737 | * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page |
| 738 | * read function |
| 739 | * @mtd: mtd info structure |
| 740 | * @chip: nand chip info structure |
| 741 | * @buf: buffer to store read data |
| 742 | * @page: page number to read |
| 743 | */ |
| 744 | static int zynq_nand_read_page_swecc(struct mtd_info *mtd, |
| 745 | struct nand_chip *chip, u8 *buf, int oob_required, int page) |
| 746 | { |
| 747 | int i, eccsize = chip->ecc.size; |
| 748 | int eccbytes = chip->ecc.bytes; |
| 749 | int eccsteps = chip->ecc.steps; |
| 750 | u8 *p = buf; |
| 751 | u8 *ecc_calc = chip->buffers->ecccalc; |
| 752 | u8 *ecc_code = chip->buffers->ecccode; |
| 753 | u32 *eccpos = chip->ecc.layout->eccpos; |
| 754 | |
| 755 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
| 756 | |
| 757 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
| 758 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
| 759 | |
| 760 | for (i = 0; i < chip->ecc.total; i++) |
| 761 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
| 762 | |
| 763 | eccsteps = chip->ecc.steps; |
| 764 | p = buf; |
| 765 | |
| 766 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
| 767 | int stat; |
| 768 | |
| 769 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
| 770 | if (stat < 0) |
| 771 | mtd->ecc_stats.failed++; |
| 772 | else |
| 773 | mtd->ecc_stats.corrected += stat; |
| 774 | } |
| 775 | return 0; |
| 776 | } |
| 777 | |
| 778 | /* |
| 779 | * zynq_nand_select_chip - Select the flash device |
| 780 | * @mtd: Pointer to the mtd_info structure |
| 781 | * @chip: Chip number to be selected |
| 782 | * |
| 783 | * This function is empty as the NAND controller handles chip select line |
| 784 | * internally based on the chip address passed in command and data phase. |
| 785 | */ |
| 786 | static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) |
| 787 | { |
| 788 | /* Not support multiple chips yet */ |
| 789 | } |
| 790 | |
| 791 | /* |
| 792 | * zynq_nand_cmd_function - Send command to NAND device |
| 793 | * @mtd: Pointer to the mtd_info structure |
| 794 | * @command: The command to be sent to the flash device |
| 795 | * @column: The column address for this command, -1 if none |
| 796 | * @page_addr: The page address for this command, -1 if none |
| 797 | */ |
| 798 | static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, |
| 799 | int column, int page_addr) |
| 800 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 801 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 802 | struct nand_drv *smc = nand_get_controller_data(chip); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 803 | const struct zynq_nand_command_format *curr_cmd = NULL; |
Siva Durga Prasad Paladugu | 2e60159 | 2017-05-25 12:15:24 +0530 | [diff] [blame] | 804 | u8 addr_cycles = 0; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 805 | struct nand_config *xnand = &smc->config; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 806 | void *cmd_addr; |
| 807 | unsigned long cmd_data = 0; |
| 808 | unsigned long cmd_phase_addr = 0; |
| 809 | unsigned long data_phase_addr = 0; |
| 810 | u8 end_cmd = 0; |
| 811 | u8 end_cmd_valid = 0; |
| 812 | u32 index; |
| 813 | |
| 814 | if (xnand->end_cmd_pending) { |
| 815 | /* Check for end command if this command request is same as the |
| 816 | * pending command then return |
| 817 | */ |
| 818 | if (xnand->end_cmd == command) { |
| 819 | xnand->end_cmd = 0; |
| 820 | xnand->end_cmd_pending = 0; |
| 821 | return; |
| 822 | } |
| 823 | } |
| 824 | |
| 825 | /* Emulate NAND_CMD_READOOB for large page device */ |
| 826 | if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) && |
| 827 | (command == NAND_CMD_READOOB)) { |
| 828 | column += mtd->writesize; |
| 829 | command = NAND_CMD_READ0; |
| 830 | } |
| 831 | |
| 832 | /* Get the command format */ |
| 833 | for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++) |
| 834 | if (command == zynq_nand_commands[index].start_cmd) |
| 835 | break; |
| 836 | |
| 837 | if (index == ARRAY_SIZE(zynq_nand_commands)) { |
| 838 | printf("%s: Unsupported start cmd %02x\n", __func__, command); |
| 839 | return; |
| 840 | } |
| 841 | curr_cmd = &zynq_nand_commands[index]; |
| 842 | |
| 843 | /* Clear interrupt */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 844 | writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 845 | |
| 846 | /* Get the command phase address */ |
| 847 | if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) |
| 848 | end_cmd_valid = 1; |
| 849 | |
Patrick van Gelder | ce9dfb9 | 2020-04-24 01:28:56 -0600 | [diff] [blame] | 850 | if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE) |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 851 | end_cmd = 0x0; |
| 852 | else |
| 853 | end_cmd = curr_cmd->end_cmd; |
| 854 | |
Siva Durga Prasad Paladugu | 2e60159 | 2017-05-25 12:15:24 +0530 | [diff] [blame] | 855 | if (command == NAND_CMD_READ0 || |
| 856 | command == NAND_CMD_SEQIN) { |
| 857 | addr_cycles = chip->onfi_params.addr_cycles & |
| 858 | ZYNQ_NAND_ROW_ADDR_CYCL_MASK; |
| 859 | addr_cycles += ((chip->onfi_params.addr_cycles & |
| 860 | ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4); |
| 861 | } else { |
| 862 | addr_cycles = curr_cmd->addr_cycles; |
| 863 | } |
| 864 | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 865 | cmd_phase_addr = (unsigned long)xnand->nand_base | |
Siva Durga Prasad Paladugu | 2e60159 | 2017-05-25 12:15:24 +0530 | [diff] [blame] | 866 | (addr_cycles << ADDR_CYCLES_SHIFT) | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 867 | (end_cmd_valid << END_CMD_VALID_SHIFT) | |
| 868 | (COMMAND_PHASE) | |
| 869 | (end_cmd << END_CMD_SHIFT) | |
| 870 | (curr_cmd->start_cmd << START_CMD_SHIFT); |
| 871 | |
| 872 | cmd_addr = (void __iomem *)cmd_phase_addr; |
| 873 | |
| 874 | /* Get the data phase address */ |
| 875 | end_cmd_valid = 0; |
| 876 | |
| 877 | data_phase_addr = (unsigned long)xnand->nand_base | |
| 878 | (0x0 << CLEAR_CS_SHIFT) | |
| 879 | (end_cmd_valid << END_CMD_VALID_SHIFT) | |
| 880 | (DATA_PHASE) | |
| 881 | (end_cmd << END_CMD_SHIFT) | |
| 882 | (0x0 << ECC_LAST_SHIFT); |
| 883 | |
| 884 | chip->IO_ADDR_R = (void __iomem *)data_phase_addr; |
| 885 | chip->IO_ADDR_W = chip->IO_ADDR_R; |
| 886 | |
| 887 | /* Command phase AXI Read & Write */ |
| 888 | if (column != -1 && page_addr != -1) { |
| 889 | /* Adjust columns for 16 bit bus width */ |
| 890 | if (chip->options & NAND_BUSWIDTH_16) |
| 891 | column >>= 1; |
| 892 | cmd_data = column; |
| 893 | if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) { |
| 894 | cmd_data |= page_addr << 16; |
| 895 | /* Another address cycle for devices > 128MiB */ |
| 896 | if (chip->chipsize > (128 << 20)) { |
| 897 | writel(cmd_data, cmd_addr); |
| 898 | cmd_data = (page_addr >> 16); |
| 899 | } |
| 900 | } else { |
| 901 | cmd_data |= page_addr << 8; |
| 902 | } |
| 903 | } else if (page_addr != -1) { /* Erase */ |
| 904 | cmd_data = page_addr; |
| 905 | } else if (column != -1) { /* Change read/write column, read id etc */ |
| 906 | /* Adjust columns for 16 bit bus width */ |
| 907 | if ((chip->options & NAND_BUSWIDTH_16) && |
| 908 | ((command == NAND_CMD_READ0) || |
| 909 | (command == NAND_CMD_SEQIN) || |
| 910 | (command == NAND_CMD_RNDOUT) || |
| 911 | (command == NAND_CMD_RNDIN))) |
| 912 | column >>= 1; |
| 913 | cmd_data = column; |
| 914 | } |
| 915 | |
| 916 | writel(cmd_data, cmd_addr); |
| 917 | |
| 918 | if (curr_cmd->end_cmd_valid) { |
| 919 | xnand->end_cmd = curr_cmd->end_cmd; |
| 920 | xnand->end_cmd_pending = 1; |
| 921 | } |
| 922 | |
| 923 | ndelay(100); |
| 924 | |
| 925 | if ((command == NAND_CMD_READ0) || |
| 926 | (command == NAND_CMD_RESET) || |
| 927 | (command == NAND_CMD_PARAM) || |
| 928 | (command == NAND_CMD_GET_FEATURES)) |
| 929 | /* wait until command is processed */ |
| 930 | nand_wait_ready(mtd); |
| 931 | } |
| 932 | |
| 933 | /* |
| 934 | * zynq_nand_read_buf - read chip data into buffer |
| 935 | * @mtd: MTD device structure |
| 936 | * @buf: buffer to store date |
| 937 | * @len: number of bytes to read |
| 938 | */ |
| 939 | static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
| 940 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 941 | struct nand_chip *chip = mtd_to_nand(mtd); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 942 | |
| 943 | /* Make sure that buf is 32 bit aligned */ |
| 944 | if (((unsigned long)buf & 0x3) != 0) { |
| 945 | if (((unsigned long)buf & 0x1) != 0) { |
| 946 | if (len) { |
| 947 | *buf = readb(chip->IO_ADDR_R); |
| 948 | buf += 1; |
| 949 | len--; |
| 950 | } |
| 951 | } |
| 952 | |
| 953 | if (((unsigned long)buf & 0x3) != 0) { |
| 954 | if (len >= 2) { |
| 955 | *(u16 *)buf = readw(chip->IO_ADDR_R); |
| 956 | buf += 2; |
| 957 | len -= 2; |
| 958 | } |
| 959 | } |
| 960 | } |
| 961 | |
| 962 | /* copy aligned data */ |
| 963 | while (len >= 4) { |
| 964 | *(u32 *)buf = readl(chip->IO_ADDR_R); |
| 965 | buf += 4; |
| 966 | len -= 4; |
| 967 | } |
| 968 | |
| 969 | /* mop up any remaining bytes */ |
| 970 | if (len) { |
| 971 | if (len >= 2) { |
| 972 | *(u16 *)buf = readw(chip->IO_ADDR_R); |
| 973 | buf += 2; |
| 974 | len -= 2; |
| 975 | } |
| 976 | if (len) |
| 977 | *buf = readb(chip->IO_ADDR_R); |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | /* |
| 982 | * zynq_nand_write_buf - write buffer to chip |
| 983 | * @mtd: MTD device structure |
| 984 | * @buf: data buffer |
| 985 | * @len: number of bytes to write |
| 986 | */ |
| 987 | static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
| 988 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 989 | struct nand_chip *chip = mtd_to_nand(mtd); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 990 | const u32 *nand = chip->IO_ADDR_W; |
| 991 | |
| 992 | /* Make sure that buf is 32 bit aligned */ |
| 993 | if (((unsigned long)buf & 0x3) != 0) { |
| 994 | if (((unsigned long)buf & 0x1) != 0) { |
| 995 | if (len) { |
| 996 | writeb(*buf, nand); |
| 997 | buf += 1; |
| 998 | len--; |
| 999 | } |
| 1000 | } |
| 1001 | |
| 1002 | if (((unsigned long)buf & 0x3) != 0) { |
| 1003 | if (len >= 2) { |
| 1004 | writew(*(u16 *)buf, nand); |
| 1005 | buf += 2; |
| 1006 | len -= 2; |
| 1007 | } |
| 1008 | } |
| 1009 | } |
| 1010 | |
| 1011 | /* copy aligned data */ |
| 1012 | while (len >= 4) { |
| 1013 | writel(*(u32 *)buf, nand); |
| 1014 | buf += 4; |
| 1015 | len -= 4; |
| 1016 | } |
| 1017 | |
| 1018 | /* mop up any remaining bytes */ |
| 1019 | if (len) { |
| 1020 | if (len >= 2) { |
| 1021 | writew(*(u16 *)buf, nand); |
| 1022 | buf += 2; |
| 1023 | len -= 2; |
| 1024 | } |
| 1025 | |
| 1026 | if (len) |
| 1027 | writeb(*buf, nand); |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | /* |
| 1032 | * zynq_nand_device_ready - Check device ready/busy line |
| 1033 | * @mtd: Pointer to the mtd_info structure |
| 1034 | * |
| 1035 | * returns: 0 on busy or 1 on ready state |
| 1036 | */ |
| 1037 | static int zynq_nand_device_ready(struct mtd_info *mtd) |
| 1038 | { |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1039 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
| 1040 | struct nand_drv *smc = nand_get_controller_data(nand_chip); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1041 | u32 csr_val; |
| 1042 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1043 | csr_val = readl(&smc->reg->csr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1044 | /* Check the raw_int_status1 bit */ |
| 1045 | if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) { |
| 1046 | /* Clear the interrupt condition */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1047 | writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1048 | return 1; |
| 1049 | } |
| 1050 | |
| 1051 | return 0; |
| 1052 | } |
| 1053 | |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 1054 | static int zynq_nand_check_is_16bit_bw_flash(void) |
| 1055 | { |
| 1056 | int is_16bit_bw = NAND_BW_UNKNOWN; |
| 1057 | int mio_num_8bit = 0, mio_num_16bit = 0; |
| 1058 | |
| 1059 | mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8"); |
| 1060 | if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) |
| 1061 | is_16bit_bw = NAND_BW_8BIT; |
| 1062 | |
| 1063 | mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16"); |
| 1064 | if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT && |
| 1065 | mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT) |
| 1066 | is_16bit_bw = NAND_BW_16BIT; |
| 1067 | |
| 1068 | return is_16bit_bw; |
| 1069 | } |
| 1070 | |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1071 | static int zynq_nand_probe(struct udevice *dev) |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1072 | { |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1073 | struct zynq_nand_info *zynq = dev_get_priv(dev); |
| 1074 | struct nand_chip *nand_chip = &zynq->nand_chip; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1075 | struct nand_drv *smc = &zynq->nand_ctrl; |
| 1076 | struct nand_config *xnand = &smc->config; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1077 | struct mtd_info *mtd; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1078 | struct resource res; |
| 1079 | ofnode of_nand; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1080 | unsigned long ecc_page_size; |
| 1081 | u8 maf_id, dev_id, i; |
| 1082 | u8 get_feature[4]; |
| 1083 | u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00}; |
| 1084 | unsigned long ecc_cfg; |
| 1085 | int ondie_ecc_enabled = 0; |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 1086 | int is_16bit_bw; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1087 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1088 | smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); |
Michal Simek | 3ba1508 | 2022-02-23 15:10:33 +0100 | [diff] [blame] | 1089 | of_nand = dev_read_subnode(dev, "nand-controller@0,0"); |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1090 | if (!ofnode_valid(of_nand)) { |
Michal Simek | 3ba1508 | 2022-02-23 15:10:33 +0100 | [diff] [blame] | 1091 | of_nand = dev_read_subnode(dev, "flash@e1000000"); |
| 1092 | if (!ofnode_valid(of_nand)) { |
| 1093 | printf("Failed to find nand node in dt\n"); |
| 1094 | return -ENODEV; |
| 1095 | } |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1096 | } |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1097 | |
Michal Simek | 4de7321 | 2020-02-25 14:40:42 +0100 | [diff] [blame] | 1098 | if (!ofnode_is_available(of_nand)) { |
| 1099 | debug("Nand node in dt disabled\n"); |
| 1100 | return dm_scan_fdt_dev(dev); |
| 1101 | } |
| 1102 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1103 | if (ofnode_read_resource(of_nand, 0, &res)) { |
| 1104 | printf("Failed to get nand resource\n"); |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1105 | return -ENODEV; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1106 | } |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1107 | |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1108 | xnand->nand_base = (void __iomem *)res.start; |
Ezequiel Garcia | 9bdba1f | 2018-01-12 15:30:55 -0300 | [diff] [blame] | 1109 | mtd = nand_to_mtd(nand_chip); |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1110 | nand_set_controller_data(nand_chip, &zynq->nand_ctrl); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1111 | |
| 1112 | /* Set address of NAND IO lines */ |
| 1113 | nand_chip->IO_ADDR_R = xnand->nand_base; |
| 1114 | nand_chip->IO_ADDR_W = xnand->nand_base; |
| 1115 | |
| 1116 | /* Set the driver entry points for MTD */ |
| 1117 | nand_chip->cmdfunc = zynq_nand_cmd_function; |
| 1118 | nand_chip->dev_ready = zynq_nand_device_ready; |
| 1119 | nand_chip->select_chip = zynq_nand_select_chip; |
| 1120 | |
| 1121 | /* If we don't set this delay driver sets 20us by default */ |
| 1122 | nand_chip->chip_delay = 30; |
| 1123 | |
| 1124 | /* Buffer read/write routines */ |
| 1125 | nand_chip->read_buf = zynq_nand_read_buf; |
| 1126 | nand_chip->write_buf = zynq_nand_write_buf; |
| 1127 | |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 1128 | is_16bit_bw = zynq_nand_check_is_16bit_bw_flash(); |
| 1129 | if (is_16bit_bw == NAND_BW_UNKNOWN) { |
| 1130 | printf("%s: Unable detect NAND based on MIO settings\n", |
| 1131 | __func__); |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1132 | return -EINVAL; |
Siva Durga Prasad Paladugu | 8597e8a | 2017-05-25 14:25:55 +0530 | [diff] [blame] | 1133 | } |
| 1134 | |
| 1135 | if (is_16bit_bw == NAND_BW_16BIT) |
| 1136 | nand_chip->options = NAND_BUSWIDTH_16; |
| 1137 | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1138 | nand_chip->bbt_options = NAND_BBT_USE_FLASH; |
| 1139 | |
| 1140 | /* Initialize the NAND flash interface on NAND controller */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1141 | if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) { |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1142 | printf("%s: nand flash init failed\n", __func__); |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1143 | return -EINVAL; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1144 | } |
| 1145 | |
| 1146 | /* first scan to find the device and get the page size */ |
| 1147 | if (nand_scan_ident(mtd, 1, NULL)) { |
| 1148 | printf("%s: nand_scan_ident failed\n", __func__); |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1149 | return -EINVAL; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1150 | } |
| 1151 | /* Send the command for reading device ID */ |
| 1152 | nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
| 1153 | nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
| 1154 | |
| 1155 | /* Read manufacturer and device IDs */ |
| 1156 | maf_id = nand_chip->read_byte(mtd); |
| 1157 | dev_id = nand_chip->read_byte(mtd); |
| 1158 | |
| 1159 | if ((maf_id == 0x2c) && ((dev_id == 0xf1) || |
| 1160 | (dev_id == 0xa1) || (dev_id == 0xb1) || |
| 1161 | (dev_id == 0xaa) || (dev_id == 0xba) || |
| 1162 | (dev_id == 0xda) || (dev_id == 0xca) || |
| 1163 | (dev_id == 0xac) || (dev_id == 0xbc) || |
| 1164 | (dev_id == 0xdc) || (dev_id == 0xcc) || |
| 1165 | (dev_id == 0xa3) || (dev_id == 0xb3) || |
| 1166 | (dev_id == 0xd3) || (dev_id == 0xc3))) { |
| 1167 | nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, |
| 1168 | ONDIE_ECC_FEATURE_ADDR, -1); |
| 1169 | for (i = 0; i < 4; i++) |
| 1170 | writeb(set_feature[i], nand_chip->IO_ADDR_W); |
| 1171 | |
| 1172 | /* Wait for 1us after writing data with SET_FEATURES command */ |
| 1173 | ndelay(1000); |
| 1174 | |
| 1175 | nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, |
| 1176 | ONDIE_ECC_FEATURE_ADDR, -1); |
| 1177 | nand_chip->read_buf(mtd, get_feature, 4); |
| 1178 | |
| 1179 | if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) { |
| 1180 | debug("%s: OnDie ECC flash\n", __func__); |
| 1181 | ondie_ecc_enabled = 1; |
| 1182 | } else { |
| 1183 | printf("%s: Unable to detect OnDie ECC\n", __func__); |
| 1184 | } |
| 1185 | } |
| 1186 | |
| 1187 | if (ondie_ecc_enabled) { |
| 1188 | /* Bypass the controller ECC block */ |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1189 | ecc_cfg = readl(&smc->reg->emcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1190 | ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK; |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1191 | writel(ecc_cfg, &smc->reg->emcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1192 | |
| 1193 | /* The software ECC routines won't work |
| 1194 | * with the SMC controller |
| 1195 | */ |
| 1196 | nand_chip->ecc.mode = NAND_ECC_HW; |
| 1197 | nand_chip->ecc.strength = 1; |
| 1198 | nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob; |
| 1199 | nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw; |
| 1200 | nand_chip->ecc.write_page = zynq_nand_write_page_raw; |
| 1201 | nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; |
| 1202 | nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; |
| 1203 | nand_chip->ecc.read_oob = zynq_nand_read_oob; |
| 1204 | nand_chip->ecc.write_oob = zynq_nand_write_oob; |
| 1205 | nand_chip->ecc.size = mtd->writesize; |
| 1206 | nand_chip->ecc.bytes = 0; |
| 1207 | |
| 1208 | /* NAND with on-die ECC supports subpage reads */ |
| 1209 | nand_chip->options |= NAND_SUBPAGE_READ; |
| 1210 | |
| 1211 | /* On-Die ECC spare bytes offset 8 is used for ECC codes */ |
Heinrich Schuchardt | 20272f3 | 2020-12-27 11:28:12 +0100 | [diff] [blame] | 1212 | nand_chip->ecc.layout = &ondie_nand_oob_64; |
| 1213 | /* Use the BBT pattern descriptors */ |
| 1214 | nand_chip->bbt_td = &bbt_main_descr; |
| 1215 | nand_chip->bbt_md = &bbt_mirror_descr; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1216 | } else { |
| 1217 | /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ |
| 1218 | nand_chip->ecc.mode = NAND_ECC_HW; |
| 1219 | nand_chip->ecc.strength = 1; |
| 1220 | nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE; |
| 1221 | nand_chip->ecc.bytes = 3; |
| 1222 | nand_chip->ecc.calculate = zynq_nand_calculate_hwecc; |
| 1223 | nand_chip->ecc.correct = zynq_nand_correct_data; |
| 1224 | nand_chip->ecc.hwctl = NULL; |
| 1225 | nand_chip->ecc.read_page = zynq_nand_read_page_hwecc; |
| 1226 | nand_chip->ecc.write_page = zynq_nand_write_page_hwecc; |
| 1227 | nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw; |
| 1228 | nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw; |
| 1229 | nand_chip->ecc.read_oob = zynq_nand_read_oob; |
| 1230 | nand_chip->ecc.write_oob = zynq_nand_write_oob; |
| 1231 | |
| 1232 | switch (mtd->writesize) { |
| 1233 | case 512: |
| 1234 | ecc_page_size = 0x1; |
| 1235 | /* Set the ECC memory config register */ |
| 1236 | writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1237 | &smc->reg->emcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1238 | break; |
| 1239 | case 1024: |
| 1240 | ecc_page_size = 0x2; |
| 1241 | /* Set the ECC memory config register */ |
| 1242 | writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1243 | &smc->reg->emcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1244 | break; |
| 1245 | case 2048: |
| 1246 | ecc_page_size = 0x3; |
| 1247 | /* Set the ECC memory config register */ |
| 1248 | writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), |
Ashok Reddy Soma | 0c3ad69 | 2019-12-27 04:47:13 -0700 | [diff] [blame] | 1249 | &smc->reg->emcr); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1250 | break; |
| 1251 | default: |
| 1252 | nand_chip->ecc.mode = NAND_ECC_SOFT; |
| 1253 | nand_chip->ecc.calculate = nand_calculate_ecc; |
| 1254 | nand_chip->ecc.correct = nand_correct_data; |
| 1255 | nand_chip->ecc.read_page = zynq_nand_read_page_swecc; |
| 1256 | nand_chip->ecc.write_page = zynq_nand_write_page_swecc; |
| 1257 | nand_chip->ecc.size = 256; |
| 1258 | break; |
| 1259 | } |
| 1260 | |
| 1261 | if (mtd->oobsize == 16) |
| 1262 | nand_chip->ecc.layout = &nand_oob_16; |
| 1263 | else if (mtd->oobsize == 64) |
| 1264 | nand_chip->ecc.layout = &nand_oob_64; |
| 1265 | else |
| 1266 | printf("%s: No oob layout found\n", __func__); |
| 1267 | } |
| 1268 | |
| 1269 | /* Second phase scan */ |
| 1270 | if (nand_scan_tail(mtd)) { |
| 1271 | printf("%s: nand_scan_tail failed\n", __func__); |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1272 | return -EINVAL; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1273 | } |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1274 | if (nand_register(0, mtd)) |
Michal Simek | d896a51 | 2020-02-25 14:51:48 +0100 | [diff] [blame] | 1275 | return -EINVAL; |
| 1276 | |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1277 | return 0; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1278 | } |
| 1279 | |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1280 | static const struct udevice_id zynq_nand_dt_ids[] = { |
| 1281 | {.compatible = "arm,pl353-smc-r2p1",}, |
| 1282 | { /* sentinel */ } |
| 1283 | }; |
| 1284 | |
| 1285 | U_BOOT_DRIVER(zynq_nand) = { |
Michal Simek | 3309308 | 2020-01-07 08:50:34 +0100 | [diff] [blame] | 1286 | .name = "zynq_nand", |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1287 | .id = UCLASS_MTD, |
| 1288 | .of_match = zynq_nand_dt_ids, |
| 1289 | .probe = zynq_nand_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 1290 | .priv_auto = sizeof(struct zynq_nand_info), |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1291 | }; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1292 | |
Ezequiel Garcia | a26ee2e | 2018-01-13 14:56:17 -0300 | [diff] [blame] | 1293 | void board_nand_init(void) |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1294 | { |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1295 | struct udevice *dev; |
| 1296 | int ret; |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1297 | |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1298 | ret = uclass_get_device_by_driver(UCLASS_MTD, |
Simon Glass | 65130cd | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 1299 | DM_DRIVER_GET(zynq_nand), &dev); |
Ashok Reddy Soma | bb8448a | 2019-12-27 04:47:12 -0700 | [diff] [blame] | 1300 | if (ret && ret != -ENODEV) |
| 1301 | pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret); |
Siva Durga Prasad Paladugu | c41d5cd | 2016-09-27 10:55:46 +0530 | [diff] [blame] | 1302 | } |