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git01.mediatek.com / filogic / uboot / 9819670c097bec86fcd7d1e34e97e0e842b72f71 / . / include / asm-sh / cpu_sh7720.h
blob: 1b393b88a607598503067e45e0dab4da37067e61 [file] [log] [blame]
Yoshihiro Shimodaad1a3a92007-12-03 22:58:45 +0900[diff] [blame]1/*
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]2 * Copyright 2007 (C)
3 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
4 *
5 * Copyright 2008 (C)
6 * Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimodaad1a3a92007-12-03 22:58:45 +0900[diff] [blame]7 *
8 * SH7720 Internal I/O register
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _ASM_CPU_SH7720_H_
27#define _ASM_CPU_SH7720_H_
28
29#define CACHE_OC_NUM_WAYS 4
30#define CCR_CACHE_INIT 0x0000000B
31
32/* EXP */
33#define TRA 0xFFFFFFD0
34#define EXPEVT 0xFFFFFFD4
35#define INTEVT 0xFFFFFFD8
36
37/* MMU */
38#define MMUCR 0xFFFFFFE0
39#define PTEH 0xFFFFFFF0
40#define PTEL 0xFFFFFFF4
41#define TTB 0xFFFFFFF8
42
43/* CACHE */
44#define CCR 0xFFFFFFEC
45
46/* INTC */
47#define IPRF 0xA4080000
48#define IPRG 0xA4080002
49#define IPRH 0xA4080004
50#define IPRI 0xA4080006
51#define IPRJ 0xA4080008
52#define IRR5 0xA4080020
53#define IRR6 0xA4080022
54#define IRR7 0xA4080024
55#define IRR8 0xA4080026
56#define IRR9 0xA4080028
57#define IRR0 0xA4140004
58#define IRR1 0xA4140006
59#define IRR2 0xA4140008
60#define IRR3 0xA414000A
61#define IRR4 0xA414000C
62#define ICR1 0xA4140010
63#define ICR2 0xA4140012
64#define PINTER 0xA4140014
65#define IPRC 0xA4140016
66#define IPRD 0xA4140018
67#define IPRE 0xA414001A
68#define ICR0 0xA414FEE0
69#define IPRA 0xA414FEE2
70#define IPRB 0xA414FEE4
71
72/* BSC */
73#define BSC_BASE 0xA4FD0000
74#define CMNCR (BSC_BASE + 0x00)
75#define CS0BCR (BSC_BASE + 0x04)
76#define CS2BCR (BSC_BASE + 0x08)
77#define CS3BCR (BSC_BASE + 0x0C)
78#define CS4BCR (BSC_BASE + 0x10)
79#define CS5ABCR (BSC_BASE + 0x14)
80#define CS5BBCR (BSC_BASE + 0x18)
81#define CS6ABCR (BSC_BASE + 0x1C)
82#define CS6BBCR (BSC_BASE + 0x20)
83#define CS0WCR (BSC_BASE + 0x24)
84#define CS2WCR (BSC_BASE + 0x28)
85#define CS3WCR (BSC_BASE + 0x2C)
86#define CS4WCR (BSC_BASE + 0x30)
87#define CS5AWCR (BSC_BASE + 0x34)
88#define CS5BWCR (BSC_BASE + 0x38)
89#define CS6AWCR (BSC_BASE + 0x3C)
90#define CS6BWCR (BSC_BASE + 0x40)
91#define SDCR (BSC_BASE + 0x44)
92#define RTCSR (BSC_BASE + 0x48)
93#define RTCNR (BSC_BASE + 0x4C)
94#define RTCOR (BSC_BASE + 0x50)
95#define SDMR2 (BSC_BASE + 0x4000)
96#define SDMR3 (BSC_BASE + 0x5000)
97
98/* DMAC */
99
100/* CPG */
101#define UCLKCR 0xA40A0008
102#define FRQCR 0xA415FF80
103
104/* LOW POWER MODE */
105
106/* TMU */
107#define TMU_BASE 0xA412FE90
108#define TSTR (TMU_BASE + 0x02)
109#define TCOR0 (TMU_BASE + 0x04)
110#define TCNT0 (TMU_BASE + 0x08)
111#define TCR0 (TMU_BASE + 0x0C)
112#define TCOR1 (TMU_BASE + 0x10)
113#define TCNT1 (TMU_BASE + 0x14)
114#define TCR1 (TMU_BASE + 0x18)
115#define TCOR2 (TMU_BASE + 0x1C)
116#define TCNT2 (TMU_BASE + 0x20)
117#define TCR2 (TMU_BASE + 0x24)
118
119/* TPU */
120#define TPU_BASE 0xA4480000
121#define TPU_TSTR (TPU_BASE + 0x00)
122#define TPU_TCR0 (TPU_BASE + 0x10)
123#define TPU_TMDR0 (TPU_BASE + 0x14)
124#define TPU_TIOR0 (TPU_BASE + 0x18)
125#define TPU_TIER0 (TPU_BASE + 0x1C)
126#define TPU_TSR0 (TPU_BASE + 0x20)
127#define TPU_TCNT0 (TPU_BASE + 0x24)
128#define TPU_TGRA0 (TPU_BASE + 0x28)
129#define TPU_TGRB0 (TPU_BASE + 0x2C)
130#define TPU_TGRC0 (TPU_BASE + 0x30)
131#define TPU_TGRD0 (TPU_BASE + 0x34)
132#define TPU_TCR1 (TPU_BASE + 0x50)
133#define TPU_TMDR1 (TPU_BASE + 0x54)
134#define TPU_TIOR1 (TPU_BASE + 0x58)
135#define TPU_TIER1 (TPU_BASE + 0x5C)
136#define TPU_TSR1 (TPU_BASE + 0x60)
137#define TPU_TCNT1 (TPU_BASE + 0x64)
138#define TPU_TGRA1 (TPU_BASE + 0x68)
139#define TPU_TGRB1 (TPU_BASE + 0x6C)
140#define TPU_TGRC1 (TPU_BASE + 0x70)
141#define TPU_TGRD1 (TPU_BASE + 0x74)
142#define TPU_TCR2 (TPU_BASE + 0x90)
143#define TPU_TMDR2 (TPU_BASE + 0x94)
144#define TPU_TIOR2 (TPU_BASE + 0x98)
145#define TPU_TIER2 (TPU_BASE + 0x9C)
146#define TPU_TSR2 (TPU_BASE + 0xB0)
147#define TPU_TCNT2 (TPU_BASE + 0xB4)
148#define TPU_TGRA2 (TPU_BASE + 0xB8)
149#define TPU_TGRB2 (TPU_BASE + 0xBC)
150#define TPU_TGRC2 (TPU_BASE + 0xC0)
151#define TPU_TGRD2 (TPU_BASE + 0xC4)
152#define TPU_TCR3 (TPU_BASE + 0xD0)
153#define TPU_TMDR3 (TPU_BASE + 0xD4)
154#define TPU_TIOR3 (TPU_BASE + 0xD8)
155#define TPU_TIER3 (TPU_BASE + 0xDC)
156#define TPU_TSR3 (TPU_BASE + 0xE0)
157#define TPU_TCNT3 (TPU_BASE + 0xE4)
158#define TPU_TGRA3 (TPU_BASE + 0xE8)
159#define TPU_TGRB3 (TPU_BASE + 0xEC)
160#define TPU_TGRC3 (TPU_BASE + 0xF0)
161#define TPU_TGRD3 (TPU_BASE + 0xF4)
162
163/* CMT */
164
165/* SIOF */
166
167/* SCIF */
168#define SCIF0_BASE 0xA4430000
169
170/* SIM */
171
172/* IrDA */
173
174/* IIC */
175
176/* LCDC */
177
178/* USBF */
179
180/* MMCIF */
181
182/* PFC */
183#define PFC_BASE 0xA4050100
184#define PACR (PFC_BASE + 0x00)
185#define PBCR (PFC_BASE + 0x02)
186#define PCCR (PFC_BASE + 0x04)
187#define PDCR (PFC_BASE + 0x06)
188#define PECR (PFC_BASE + 0x08)
189#define PFCR (PFC_BASE + 0x0A)
190#define PGCR (PFC_BASE + 0x0C)
191#define PHCR (PFC_BASE + 0x0E)
192#define PJCR (PFC_BASE + 0x10)
193#define PKCR (PFC_BASE + 0x12)
194#define PLCR (PFC_BASE + 0x14)
195#define PMCR (PFC_BASE + 0x16)
196#define PPCR (PFC_BASE + 0x18)
197#define PRCR (PFC_BASE + 0x1A)
198#define PSCR (PFC_BASE + 0x1C)
199#define PTCR (PFC_BASE + 0x1E)
200#define PUCR (PFC_BASE + 0x20)
201#define PVCR (PFC_BASE + 0x22)
202#define PSELA (PFC_BASE + 0x24)
203#define PSELB (PFC_BASE + 0x26)
204#define PSELC (PFC_BASE + 0x28)
205#define PSELD (PFC_BASE + 0x2A)
206
207/* I/O Port */
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]208#define PORT_BASE 0xA4050100
209#define PADR (PORT_BASE + 0x40)
210#define PBDR (PORT_BASE + 0x42)
211#define PCDR (PORT_BASE + 0x44)
212#define PDDR (PORT_BASE + 0x46)
213#define PEDR (PORT_BASE + 0x48)
214#define PFDR (PORT_BASE + 0x4A)
215#define PGDR (PORT_BASE + 0x4C)
216#define PHDR (PORT_BASE + 0x4E)
217#define PJDR (PORT_BASE + 0x50)
218#define PKDR (PORT_BASE + 0x52)
219#define PLDR (PORT_BASE + 0x54)
220#define PMDR (PORT_BASE + 0x56)
221#define PPDR (PORT_BASE + 0x58)
222#define PRDR (PORT_BASE + 0x5A)
223#define PSDR (PORT_BASE + 0x5C)
224#define PTDR (PORT_BASE + 0x5E)
225#define PUDR (PORT_BASE + 0x60)
226#define PVDR (PORT_BASE + 0x62)
Yoshihiro Shimodaad1a3a92007-12-03 22:58:45 +0900[diff] [blame]227
228/* H-UDI */
229
230#endif /* _ASM_CPU_SH7720_H_ */