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Steve Sakoman1b3dd5d2010-06-08 13:07:46 -07001/*
2 * (C) Copyright 2010
3 * Texas Instruments Incorporated.
4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com>
6 *
7 * Configuration settings for the TI SDP4430 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP44XX 1 /* which is a 44XX */
37#define CONFIG_OMAP4430 1 /* which is in a 4430 */
38#define CONFIG_4430SDP 1 /* working with SDP */
Steve Sakoman9bb65b52010-07-15 13:43:10 -070039#define CONFIG_ARCH_CPU_INIT
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -070040
41/* Get CPU defs */
42#include <asm/arch/cpu.h>
43#include <asm/arch/omap4.h>
44
45/* Display CPU and Board Info */
46#define CONFIG_DISPLAY_CPUINFO 1
47#define CONFIG_DISPLAY_BOARDINFO 1
48
49/* Keep L2 Cache Disabled */
50#define CONFIG_L2_OFF 1
51
52/* Clock Defines */
53#define V_OSCK 38400000 /* Clock output from T2 */
54#define V_SCLK V_OSCK
55
56#undef CONFIG_USE_IRQ /* no support for IRQs */
57#define CONFIG_MISC_INIT_R
58
59#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
60#define CONFIG_SETUP_MEMORY_TAGS 1
61#define CONFIG_INITRD_TAG 1
62#define CONFIG_REVISION_TAG 1
63
64/*
65 * Size of malloc() pool
Sukumar Ghoraibbc08c42010-09-14 13:52:34 +053066 * Total Size Environment - 128k
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -070067 * Malloc - add 256k
68 */
Sukumar Ghoraibbc08c42010-09-14 13:52:34 +053069#define CONFIG_ENV_SIZE (128 << 10)
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -070070#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
71#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
72 /* initial data */
73/* Vector Base */
74#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
75
76/*
77 * Hardware drivers
78 */
79
80/*
81 * serial port - NS16550 compatible
82 */
83#define V_NS16550_CLK 48000000
84
85#define CONFIG_SYS_NS16550
86#define CONFIG_SYS_NS16550_SERIAL
87#define CONFIG_SYS_NS16550_REG_SIZE (-4)
88#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
89#define CONFIG_CONS_INDEX 3
90#define CONFIG_SYS_NS16550_COM3 UART3_BASE
91
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -070092#define CONFIG_BAUDRATE 115200
93#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
94 115200}
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -070095/* I2C */
96#define CONFIG_HARD_I2C 1
97#define CONFIG_SYS_I2C_SPEED 100000
98#define CONFIG_SYS_I2C_SLAVE 1
99#define CONFIG_SYS_I2C_BUS 0
100#define CONFIG_SYS_I2C_BUS_SELECT 1
101#define CONFIG_DRIVER_OMAP34XX_I2C 1
102#define CONFIG_I2C_MULTI_BUS 1
103
Steve Sakomanf8f7c952010-07-15 12:53:42 -0700104/* TWL6030 */
105#define CONFIG_TWL6030_POWER 1
106
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700107/* MMC */
Sukumar Ghorai7d99f692010-09-18 20:59:54 -0700108#define CONFIG_GENERIC_MMC 1
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700109#define CONFIG_MMC 1
Sukumar Ghorai7d99f692010-09-18 20:59:54 -0700110#define CONFIG_OMAP_HSMMC 1
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700111#define CONFIG_SYS_MMC_SET_DEV 1
112#define CONFIG_DOS_PARTITION 1
113
Sukumar Ghoraibbc08c42010-09-14 13:52:34 +0530114/* MMC ENV related defines */
115#define CONFIG_ENV_IS_IN_MMC 1
116#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
117#define CONFIG_ENV_OFFSET 0xE0000
118
Steve Sakoman69c50e82010-06-25 12:44:33 -0700119/* USB */
120#define CONFIG_MUSB_UDC 1
121#define CONFIG_USB_OMAP3 1
122
123/* USB device configuration */
124#define CONFIG_USB_DEVICE 1
125#define CONFIG_USB_TTY 1
126#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
Steve Sakoman69c50e82010-06-25 12:44:33 -0700127
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700128/* Flash */
129#define CONFIG_SYS_NO_FLASH 1
130
131/* commands to include */
132#include <config_cmd_default.h>
133
134/* Enabled commands */
135#define CONFIG_CMD_EXT2 /* EXT2 Support */
136#define CONFIG_CMD_FAT /* FAT support */
137#define CONFIG_CMD_I2C /* I2C serial bus support */
138#define CONFIG_CMD_MMC /* MMC support */
Sukumar Ghoraibbc08c42010-09-14 13:52:34 +0530139#define CONFIG_CMD_SAVEENV
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700140
141/* Disabled commands */
142#undef CONFIG_CMD_NET
143#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
144#undef CONFIG_CMD_IMLS /* List all found images */
145
146/*
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700147 * Environment setup
148 */
149
Steve Sakoman9abea222010-07-07 15:25:25 -0700150#define CONFIG_BOOTDELAY 3
151
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700152#define CONFIG_ENV_OVERWRITE
153
154#define CONFIG_EXTRA_ENV_SETTINGS \
155 "loadaddr=0x82000000\0" \
156 "console=ttyS2,115200n8\0" \
Steve Sakoman69c50e82010-06-25 12:44:33 -0700157 "usbtty=cdc_acm\0" \
Steve Sakoman9abea222010-07-07 15:25:25 -0700158 "vram=16M\0" \
Sukumar Ghorai7d99f692010-09-18 20:59:54 -0700159 "mmcdev=0\0" \
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700160 "mmcroot=/dev/mmcblk0p2 rw\0" \
161 "mmcrootfstype=ext3 rootwait\0" \
162 "mmcargs=setenv bootargs console=${console} " \
Steve Sakoman9abea222010-07-07 15:25:25 -0700163 "vram=${vram} " \
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700164 "root=${mmcroot} " \
165 "rootfstype=${mmcrootfstype}\0" \
166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
167 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
168 "source ${loadaddr}\0" \
169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
170 "mmcboot=echo Booting from mmc${mmcdev} ...; " \
171 "run mmcargs; " \
172 "bootm ${loadaddr}\0" \
173
174#define CONFIG_BOOTCOMMAND \
Sukumar Ghorai7d99f692010-09-18 20:59:54 -0700175 "if mmc rescan ${mmcdev}; then " \
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700176 "if run loadbootscript; then " \
177 "run bootscript; " \
178 "else " \
179 "if run loaduimage; then " \
180 "run mmcboot; " \
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700181 "fi; " \
182 "fi; " \
183 "fi"
184
185#define CONFIG_AUTO_COMPLETE 1
186
187/*
188 * Miscellaneous configurable options
189 */
190
191#define CONFIG_SYS_LONGHELP /* undef to save memory */
192#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
193#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
194#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
195#define CONFIG_SYS_CBSIZE 256
196/* Print Buffer Size */
197#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
198 sizeof(CONFIG_SYS_PROMPT) + 16)
199#define CONFIG_SYS_MAXARGS 16
200/* Boot Argument Buffer Size */
201#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
202
203/*
204 * memtest setup
205 */
206#define CONFIG_SYS_MEMTEST_START 0x80000000
207#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
208
209/* Default load address */
210#define CONFIG_SYS_LOAD_ADDR 0x80000000
211
212/* Use General purpose timer 1 */
Steve Sakoman58657e62010-07-20 14:56:07 -0700213#define CONFIG_SYS_TIMERBASE GPT2_BASE
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700214#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
215#define CONFIG_SYS_HZ 1000
216
217/*
218 * Stack sizes
219 *
220 * The stack sizes are set up in start.S using the settings below
221 */
222#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
223#ifdef CONFIG_USE_IRQ
224#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
225#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
226#endif
227
228/*
229 * SDRAM Memory Map
230 * Even though we use two CS all the memory
231 * is mapped to one contiguous block
232 */
233#define CONFIG_NR_DRAM_BANKS 1
234
Steve Sakoman97c57f12010-09-29 20:59:51 -0700235#define CONFIG_SYS_SDRAM_BASE 0x80000000
236#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
237
Steve Sakoman1b3dd5d2010-06-08 13:07:46 -0700238#endif /* __CONFIG_H */