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git01.mediatek.com / filogic / uboot / 97aaa98ca411bfeeaca412b6ce80681ed405dffe / . / arch / arm / dts / imx6qdl-gw53xx.dtsi
blob: 9deec7e352d5a7d3941ee039e599bee4dcc30f20 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
18 ssi0 = &ssi1;
19 usb0 = &usbh1;
20 usb1 = &usbotg;
21 };
22
23 chosen {
24 bootargs = "console=ttymxc1,115200";
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm4 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <7>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 user-pb {
40 label = "user_pb";
41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
42 linux,code = <BTN_0>;
43 };
44
45 user-pb1x {
46 label = "user_pb1x";
47 linux,code = <BTN_1>;
48 interrupt-parent = <&gsc>;
49 interrupts = <0>;
50 };
51
52 key-erased {
53 label = "key-erased";
54 linux,code = <BTN_2>;
55 interrupt-parent = <&gsc>;
56 interrupts = <1>;
57 };
58
59 eeprom-wp {
60 label = "eeprom_wp";
61 linux,code = <BTN_3>;
62 interrupt-parent = <&gsc>;
63 interrupts = <2>;
64 };
65
66 tamper {
67 label = "tamper";
68 linux,code = <BTN_4>;
69 interrupt-parent = <&gsc>;
70 interrupts = <5>;
71 };
72
73 switch-hold {
74 label = "switch_hold";
75 linux,code = <BTN_5>;
76 interrupt-parent = <&gsc>;
77 interrupts = <7>;
78 };
79 };
80
81 leds {
82 compatible = "gpio-leds";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_gpio_leds>;
85
86 led0: user1 {
87 label = "user1";
88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
89 default-state = "on";
90 linux,default-trigger = "heartbeat";
91 };
92
93 led1: user2 {
94 label = "user2";
95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
96 default-state = "off";
97 };
98
99 led2: user3 {
100 label = "user3";
101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
102 default-state = "off";
103 };
104 };
105
106 memory@10000000 {
107 device_type = "memory";
108 reg = <0x10000000 0x40000000>;
109 };
110
111 pps {
112 compatible = "pps-gpio";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_pps>;
115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 status = "okay";
117 };
118
119 reg_1p0v: regulator-1p0v {
120 compatible = "regulator-fixed";
121 regulator-name = "1P0V";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 reg_3p3v: regulator-3p3v {
128 compatible = "regulator-fixed";
129 regulator-name = "3P3V";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_usb_h1_vbus: regulator-usb-h1-vbus {
136 compatible = "regulator-fixed";
137 regulator-name = "usb_h1_vbus";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
140 regulator-always-on;
141 };
142
143 reg_usb_otg_vbus: regulator-usb-otg-vbus {
144 compatible = "regulator-fixed";
145 regulator-name = "usb_otg_vbus";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
148 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
149 enable-active-high;
150 };
151
152 sound {
153 compatible = "fsl,imx6q-ventana-sgtl5000",
154 "fsl,imx-audio-sgtl5000";
155 model = "sgtl5000-audio";
156 ssi-controller = <&ssi1>;
157 audio-codec = <&codec>;
158 audio-routing =
159 "MIC_IN", "Mic Jack",
160 "Mic Jack", "Mic Bias",
161 "Headphone Jack", "HP_OUT";
162 mux-int-port = <1>;
163 mux-ext-port = <4>;
164 };
165};
166
167&audmux {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_audmux>;
170 status = "okay";
171};
172
173&can1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_flexcan1>;
176 status = "okay";
177};
178
179&clks {
180 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
181 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
182 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
183 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
184};
185
186&fec {
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_enet>;
189 phy-mode = "rgmii-id";
190 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
191 status = "okay";
192};
193
194&gpmi {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_gpmi_nand>;
197 status = "okay";
198};
199
200&hdmi {
201 ddc-i2c-bus = <&i2c3>;
202 status = "okay";
203};
204
205&i2c1 {
206 clock-frequency = <100000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_i2c1>;
209 status = "okay";
210
211 gsc: gsc@20 {
212 compatible = "gw,gsc";
213 reg = <0x20>;
214 interrupt-parent = <&gpio1>;
215 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
216 interrupt-controller;
217 #interrupt-cells = <1>;
218 #size-cells = <0>;
219
220 adc {
221 compatible = "gw,gsc-adc";
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 channel@0 {
226 gw,mode = <0>;
227 reg = <0x00>;
228 label = "temp";
229 };
230
231 channel@2 {
232 gw,mode = <1>;
233 reg = <0x02>;
234 label = "vdd_vin";
235 };
236
237 channel@5 {
238 gw,mode = <1>;
239 reg = <0x05>;
240 label = "vdd_3p3";
241 };
242
243 channel@8 {
244 gw,mode = <1>;
245 reg = <0x08>;
246 label = "vdd_bat";
247 };
248
249 channel@b {
250 gw,mode = <1>;
251 reg = <0x0b>;
252 label = "vdd_5p0";
253 };
254
255 channel@e {
256 gw,mode = <1>;
257 reg = <0xe>;
258 label = "vdd_arm";
259 };
260
261 channel@11 {
262 gw,mode = <1>;
263 reg = <0x11>;
264 label = "vdd_soc";
265 };
266
267 channel@14 {
268 gw,mode = <1>;
269 reg = <0x14>;
270 label = "vdd_3p0";
271 };
272
273 channel@17 {
274 gw,mode = <1>;
275 reg = <0x17>;
276 label = "vdd_1p5";
277 };
278
279 channel@1d {
280 gw,mode = <1>;
281 reg = <0x1d>;
282 label = "vdd_1p8";
283 };
284
285 channel@20 {
286 gw,mode = <1>;
287 reg = <0x20>;
288 label = "vdd_1p0";
289 };
290
291 channel@23 {
292 gw,mode = <1>;
293 reg = <0x23>;
294 label = "vdd_2p5";
295 };
296
297 channel@26 {
298 gw,mode = <1>;
299 reg = <0x26>;
300 label = "vdd_gps";
301 };
302
303 channel@29 {
304 gw,mode = <1>;
305 reg = <0x29>;
306 label = "vdd_an1";
307 };
308 };
309 };
310
311 gsc_gpio: gpio@23 {
312 compatible = "nxp,pca9555";
313 reg = <0x23>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-parent = <&gsc>;
317 interrupts = <4>;
318 };
319
320 eeprom1: eeprom@50 {
321 compatible = "atmel,24c02";
322 reg = <0x50>;
323 pagesize = <16>;
324 };
325
326 eeprom2: eeprom@51 {
327 compatible = "atmel,24c02";
328 reg = <0x51>;
329 pagesize = <16>;
330 };
331
332 eeprom3: eeprom@52 {
333 compatible = "atmel,24c02";
334 reg = <0x52>;
335 pagesize = <16>;
336 };
337
338 eeprom4: eeprom@53 {
339 compatible = "atmel,24c02";
340 reg = <0x53>;
341 pagesize = <16>;
342 };
343
344 rtc: ds1672@68 {
345 compatible = "dallas,ds1672";
346 reg = <0x68>;
347 };
348};
349
350&i2c2 {
351 clock-frequency = <100000>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_i2c2>;
354 status = "okay";
355
356 ltc3676: pmic@3c {
357 compatible = "lltc,ltc3676";
358 reg = <0x3c>;
359 interrupt-parent = <&gpio1>;
360 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
361
362 regulators {
363 /* VDD_SOC (1+R1/R2 = 1.635) */
364 reg_vdd_soc: sw1 {
365 regulator-name = "vddsoc";
366 regulator-min-microvolt = <674400>;
367 regulator-max-microvolt = <1308000>;
368 lltc,fb-voltage-divider = <127000 200000>;
369 regulator-ramp-delay = <7000>;
370 regulator-boot-on;
371 regulator-always-on;
372 };
373
374 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
375 reg_1p8v: sw2 {
376 regulator-name = "vdd1p8";
377 regulator-min-microvolt = <1033310>;
378 regulator-max-microvolt = <2004000>;
379 lltc,fb-voltage-divider = <301000 200000>;
380 regulator-ramp-delay = <7000>;
381 regulator-boot-on;
382 regulator-always-on;
383 };
384
385 /* VDD_ARM (1+R1/R2 = 1.635) */
386 reg_vdd_arm: sw3 {
387 regulator-name = "vddarm";
388 regulator-min-microvolt = <674400>;
389 regulator-max-microvolt = <1308000>;
390 lltc,fb-voltage-divider = <127000 200000>;
391 regulator-ramp-delay = <7000>;
392 regulator-boot-on;
393 regulator-always-on;
394 };
395
396 /* VDD_DDR (1+R1/R2 = 2.105) */
397 reg_vdd_ddr: sw4 {
398 regulator-name = "vddddr";
399 regulator-min-microvolt = <868310>;
400 regulator-max-microvolt = <1684000>;
401 lltc,fb-voltage-divider = <221000 200000>;
402 regulator-ramp-delay = <7000>;
403 regulator-boot-on;
404 regulator-always-on;
405 };
406
407 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
408 reg_2p5v: ldo2 {
409 regulator-name = "vdd2p5";
410 regulator-min-microvolt = <2490375>;
411 regulator-max-microvolt = <2490375>;
412 lltc,fb-voltage-divider = <487000 200000>;
413 regulator-boot-on;
414 regulator-always-on;
415 };
416
417 /* VDD_AUD_1P8: Audio codec */
418 reg_aud_1p8v: ldo3 {
419 regulator-name = "vdd1p8a";
420 regulator-min-microvolt = <1800000>;
421 regulator-max-microvolt = <1800000>;
422 regulator-boot-on;
423 };
424
425 /* VDD_HIGH (1+R1/R2 = 4.17) */
426 reg_3p0v: ldo4 {
427 regulator-name = "vdd3p0";
428 regulator-min-microvolt = <3023250>;
429 regulator-max-microvolt = <3023250>;
430 lltc,fb-voltage-divider = <634000 200000>;
431 regulator-boot-on;
432 regulator-always-on;
433 };
434 };
435 };
436};
437
438&i2c3 {
439 clock-frequency = <100000>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_i2c3>;
442 status = "okay";
443
444 codec: sgtl5000@a {
445 compatible = "fsl,sgtl5000";
446 reg = <0x0a>;
447 clocks = <&clks IMX6QDL_CLK_CKO>;
448 VDDA-supply = <&reg_1p8v>;
449 VDDIO-supply = <&reg_3p3v>;
450 };
451
452 touchscreen: egalax_ts@4 {
453 compatible = "eeti,egalax_ts";
454 reg = <0x04>;
455 interrupt-parent = <&gpio1>;
456 interrupts = <11 2>;
457 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
458 };
459
460 accel@1e {
461 compatible = "nxp,fxos8700";
462 reg = <0x1e>;
463 };
464};
465
466&ldb {
467 status = "okay";
468
469 lvds-channel@0 {
470 fsl,data-mapping = "spwg";
471 fsl,data-width = <18>;
472 status = "okay";
473
474 display-timings {
475 native-mode = <&timing0>;
476 timing0: hsd100pxn1 {
477 clock-frequency = <65000000>;
478 hactive = <1024>;
479 vactive = <768>;
480 hback-porch = <220>;
481 hfront-porch = <40>;
482 vback-porch = <21>;
483 vfront-porch = <7>;
484 hsync-len = <60>;
485 vsync-len = <10>;
486 };
487 };
488 };
489};
490
491&pcie {
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_pcie>;
494 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
495 status = "okay";
496};
497
498&pwm2 {
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
501 status = "disabled";
502};
503
504&pwm3 {
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
507 status = "disabled";
508};
509
510&pwm4 {
511 #pwm-cells = <2>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_pwm4>;
514 status = "okay";
515};
516
517&ssi1 {
518 status = "okay";
519};
520
521&uart1 {
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_uart1>;
524 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
525 status = "okay";
526};
527
528&uart2 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_uart2>;
531 status = "okay";
532};
533
534&uart5 {
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_uart5>;
537 status = "okay";
538};
539
540&usbotg {
541 vbus-supply = <&reg_usb_otg_vbus>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_usbotg>;
544 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]545 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]546 status = "okay";
547};
548
549&usbh1 {
550 vbus-supply = <&reg_usb_h1_vbus>;
551 status = "okay";
552};
553
554&usdhc3 {
555 pinctrl-names = "default", "state_100mhz", "state_200mhz";
556 pinctrl-0 = <&pinctrl_usdhc3>;
557 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
558 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
559 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
560 vmmc-supply = <&reg_3p3v>;
561 no-1-8-v; /* firmware will remove if board revision supports */
562 status = "okay";
563};
564
565&wdog1 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_wdog>;
568 fsl,ext-reset-output;
569};
570
571&iomuxc {
572 pinctrl_audmux: audmuxgrp {
573 fsl,pins = <
574 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
575 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
576 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
577 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
578 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
579 >;
580 };
581
582 pinctrl_enet: enetgrp {
583 fsl,pins = <
584 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
585 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
586 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
587 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
588 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
589 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
590 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
591 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
592 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
593 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
594 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
595 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
596 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
597 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
598 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
599 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
600 >;
601 };
602
603 pinctrl_flexcan1: flexcan1grp {
604 fsl,pins = <
605 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
606 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
607 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
608 >;
609 };
610
611 pinctrl_gpio_leds: gpioledsgrp {
612 fsl,pins = <
613 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
614 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
615 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
616 >;
617 };
618
619 pinctrl_gpmi_nand: gpminandgrp {
620 fsl,pins = <
621 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
622 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
623 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
624 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
625 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
626 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
627 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
628 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
629 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
630 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
631 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
632 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
633 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
634 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
635 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
636 >;
637 };
638
639 pinctrl_i2c1: i2c1grp {
640 fsl,pins = <
641 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
642 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
643 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
644 >;
645 };
646
647 pinctrl_i2c2: i2c2grp {
648 fsl,pins = <
649 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
650 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
651 >;
652 };
653
654 pinctrl_i2c3: i2c3grp {
655 fsl,pins = <
656 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
657 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
658 >;
659 };
660
661 pinctrl_pcie: pciegrp {
662 fsl,pins = <
663 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
664 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
665 >;
666 };
667
668 pinctrl_pmic: pmicgrp {
669 fsl,pins = <
670 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
671 >;
672 };
673
674 pinctrl_pps: ppsgrp {
675 fsl,pins = <
676 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
677 >;
678 };
679
680 pinctrl_pwm2: pwm2grp {
681 fsl,pins = <
682 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
683 >;
684 };
685
686 pinctrl_pwm3: pwm3grp {
687 fsl,pins = <
688 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
689 >;
690 };
691
692 pinctrl_pwm4: pwm4grp {
693 fsl,pins = <
694 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
695 >;
696 };
697
698 pinctrl_uart1: uart1grp {
699 fsl,pins = <
700 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
701 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
702 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
703 >;
704 };
705
706 pinctrl_uart2: uart2grp {
707 fsl,pins = <
708 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
709 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
710 >;
711 };
712
713 pinctrl_uart5: uart5grp {
714 fsl,pins = <
715 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
716 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
717 >;
718 };
719
720 pinctrl_usbotg: usbotggrp {
721 fsl,pins = <
722 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
723 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
724 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
725 >;
726 };
727
728 pinctrl_usdhc3: usdhc3grp {
729 fsl,pins = <
730 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
731 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
732 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
733 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
734 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
735 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
736 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
737 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
738 >;
739 };
740
741 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
742 fsl,pins = <
743 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
744 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
745 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
746 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
747 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
748 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
749 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
750 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
751 >;
752 };
753
754 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
755 fsl,pins = <
756 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
757 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
758 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
759 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
760 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
761 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
762 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
763 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
764 >;
765 };
766
767 pinctrl_wdog: wdoggrp {
768 fsl,pins = <
769 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
770 >;
771 };
772};