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git01.mediatek.com / filogic / uboot / 97979a266a25d372b266ac4435cfe49622f4c9ab / . / test / dm / test.dts
blob: 84024a44a3f0368c5cea2e983a02d25465969482 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]11 i2c0 = "/i2c@0";
12 spi0 = "/spi@0";
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]13 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 testbus3 = "/some-bus";
15 testfdt0 = "/some-bus/c-test@0";
16 testfdt1 = "/some-bus/c-test@1";
17 testfdt3 = "/b-test";
18 testfdt5 = "/some-bus/c-test@5";
19 testfdt8 = "/a-test";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]20 };
21
22 uart0: serial {
23 compatible = "sandbox,serial";
24 u-boot,dm-pre-reloc;
25 };
26
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]27 a-test {
28 reg = <0>;
29 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]30 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]31 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]32 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]33 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
34 <0>, <&gpio_a 12>;
35 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
36 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
37 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]38 };
39
40 junk {
41 reg = <1>;
42 compatible = "not,compatible";
43 };
44
45 no-compatible {
46 reg = <2>;
47 };
48
49 b-test {
50 reg = <3>;
51 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]52 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]53 ping-add = <3>;
54 };
55
56 some-bus {
57 #address-cells = <1>;
58 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]59 compatible = "denx,u-boot-test-bus";
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]60 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]61 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]62 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]63 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]64 compatible = "denx,u-boot-fdt-test";
65 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]66 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]67 ping-add = <5>;
68 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 c-test@0 {
70 compatible = "denx,u-boot-fdt-test";
71 reg = <0>;
72 ping-expect = <6>;
73 ping-add = <6>;
74 };
75 c-test@1 {
76 compatible = "denx,u-boot-fdt-test";
77 reg = <1>;
78 ping-expect = <7>;
79 ping-add = <7>;
80 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]81 };
82
83 d-test {
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]84 reg = <3>;
85 ping-expect = <6>;
86 ping-add = <6>;
87 compatible = "google,another-fdt-test";
88 };
89
90 e-test {
91 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]92 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]93 ping-add = <6>;
94 compatible = "google,another-fdt-test";
95 };
96
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]97 f-test {
98 compatible = "denx,u-boot-fdt-test";
99 };
100
101 g-test {
102 compatible = "denx,u-boot-fdt-test";
103 };
104
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]105 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]106 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]107 gpio-controller;
108 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]109 gpio-bank-name = "a";
110 num-gpios = <20>;
111 };
112
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]113 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]114 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]115 gpio-controller;
116 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]117 gpio-bank-name = "b";
118 num-gpios = <10>;
119 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]120
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]121 i2c@0 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 reg = <0>;
125 compatible = "sandbox,i2c";
126 clock-frequency = <100000>;
127 eeprom@2c {
128 reg = <0x2c>;
129 compatible = "i2c-eeprom";
130 emul {
131 compatible = "sandbox,i2c-eeprom";
132 sandbox,filename = "i2c.bin";
133 sandbox,size = <256>;
134 };
135 };
136 };
137
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]138 spi@0 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <0>;
142 compatible = "sandbox,spi";
143 cs-gpios = <0>, <&gpio_a 0>;
144 spi.bin@0 {
145 reg = <0>;
146 compatible = "spansion,m25p16", "spi-flash";
147 spi-max-frequency = <40000000>;
148 sandbox,filename = "spi.bin";
149 };
150 };
151
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]152};