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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / src / riscv / thead / th1520.dtsi
blob: 3c9974062c206b870ebe85b91da2a04e5bc7b879 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 Alibaba Group Holding Limited.
4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 compatible = "thead,th1520";
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus: cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
18
19 c910_0: cpu@0 {
20 compatible = "thead,c910", "riscv";
21 device_type = "cpu";
22 riscv,isa = "rv64imafdc";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
25 "zifencei", "zihpm";
26 reg = <0>;
27 i-cache-block-size = <64>;
28 i-cache-size = <65536>;
29 i-cache-sets = <512>;
30 d-cache-block-size = <64>;
31 d-cache-size = <65536>;
32 d-cache-sets = <512>;
33 next-level-cache = <&l2_cache>;
34 mmu-type = "riscv,sv39";
35
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 };
41 };
42
43 c910_1: cpu@1 {
44 compatible = "thead,c910", "riscv";
45 device_type = "cpu";
46 riscv,isa = "rv64imafdc";
47 riscv,isa-base = "rv64i";
48 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
49 "zifencei", "zihpm";
50 reg = <1>;
51 i-cache-block-size = <64>;
52 i-cache-size = <65536>;
53 i-cache-sets = <512>;
54 d-cache-block-size = <64>;
55 d-cache-size = <65536>;
56 d-cache-sets = <512>;
57 next-level-cache = <&l2_cache>;
58 mmu-type = "riscv,sv39";
59
60 cpu1_intc: interrupt-controller {
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 };
65 };
66
67 c910_2: cpu@2 {
68 compatible = "thead,c910", "riscv";
69 device_type = "cpu";
70 riscv,isa = "rv64imafdc";
71 riscv,isa-base = "rv64i";
72 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
73 "zifencei", "zihpm";
74 reg = <2>;
75 i-cache-block-size = <64>;
76 i-cache-size = <65536>;
77 i-cache-sets = <512>;
78 d-cache-block-size = <64>;
79 d-cache-size = <65536>;
80 d-cache-sets = <512>;
81 next-level-cache = <&l2_cache>;
82 mmu-type = "riscv,sv39";
83
84 cpu2_intc: interrupt-controller {
85 compatible = "riscv,cpu-intc";
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 };
89 };
90
91 c910_3: cpu@3 {
92 compatible = "thead,c910", "riscv";
93 device_type = "cpu";
94 riscv,isa = "rv64imafdc";
95 riscv,isa-base = "rv64i";
96 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
97 "zifencei", "zihpm";
98 reg = <3>;
99 i-cache-block-size = <64>;
100 i-cache-size = <65536>;
101 i-cache-sets = <512>;
102 d-cache-block-size = <64>;
103 d-cache-size = <65536>;
104 d-cache-sets = <512>;
105 next-level-cache = <&l2_cache>;
106 mmu-type = "riscv,sv39";
107
108 cpu3_intc: interrupt-controller {
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 };
113 };
114
115 l2_cache: l2-cache {
116 compatible = "cache";
117 cache-block-size = <64>;
118 cache-level = <2>;
119 cache-size = <1048576>;
120 cache-sets = <1024>;
121 cache-unified;
122 };
123 };
124
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]125 pmu {
126 compatible = "riscv,pmu";
127 riscv,event-to-mhpmcounters =
128 <0x00003 0x00003 0x0007fff8>,
129 <0x00004 0x00004 0x0007fff8>,
130 <0x00005 0x00005 0x0007fff8>,
131 <0x00006 0x00006 0x0007fff8>,
132 <0x00007 0x00007 0x0007fff8>,
133 <0x00008 0x00008 0x0007fff8>,
134 <0x00009 0x00009 0x0007fff8>,
135 <0x0000a 0x0000a 0x0007fff8>,
136 <0x10000 0x10000 0x0007fff8>,
137 <0x10001 0x10001 0x0007fff8>,
138 <0x10002 0x10002 0x0007fff8>,
139 <0x10003 0x10003 0x0007fff8>,
140 <0x10010 0x10010 0x0007fff8>,
141 <0x10011 0x10011 0x0007fff8>,
142 <0x10012 0x10012 0x0007fff8>,
143 <0x10013 0x10013 0x0007fff8>;
144 riscv,event-to-mhpmevent =
145 <0x00003 0x00000000 0x00000001>,
146 <0x00004 0x00000000 0x00000002>,
147 <0x00006 0x00000000 0x00000006>,
148 <0x00005 0x00000000 0x00000007>,
149 <0x00007 0x00000000 0x00000008>,
150 <0x00008 0x00000000 0x00000009>,
151 <0x00009 0x00000000 0x0000000a>,
152 <0x0000a 0x00000000 0x0000000b>,
153 <0x10000 0x00000000 0x0000000c>,
154 <0x10001 0x00000000 0x0000000d>,
155 <0x10002 0x00000000 0x0000000e>,
156 <0x10003 0x00000000 0x0000000f>,
157 <0x10010 0x00000000 0x00000010>,
158 <0x10011 0x00000000 0x00000011>,
159 <0x10012 0x00000000 0x00000012>,
160 <0x10013 0x00000000 0x00000013>;
161 riscv,raw-event-to-mhpmcounters =
162 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
163 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
164 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
165 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
166 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
167 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
168 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
169 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
170 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
171 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
172 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
173 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
174 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
175 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
176 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
177 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
178 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
179 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
180 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
181 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
182 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
183 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
184 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
185 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
186 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
187 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
188 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
189 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
190 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
191 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
192 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
193 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
194 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
195 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
196 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
197 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
198 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
199 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
200 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
201 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
202 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
203 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
204 };
205
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]206 osc: oscillator {
207 compatible = "fixed-clock";
208 clock-output-names = "osc_24m";
209 #clock-cells = <0>;
210 };
211
212 osc_32k: 32k-oscillator {
213 compatible = "fixed-clock";
214 clock-output-names = "osc_32k";
215 #clock-cells = <0>;
216 };
217
218 apb_clk: apb-clk-clock {
219 compatible = "fixed-clock";
220 clock-output-names = "apb_clk";
221 #clock-cells = <0>;
222 };
223
224 uart_sclk: uart-sclk-clock {
225 compatible = "fixed-clock";
226 clock-output-names = "uart_sclk";
227 #clock-cells = <0>;
228 };
229
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]230 sdhci_clk: sdhci-clock {
231 compatible = "fixed-clock";
232 clock-frequency = <198000000>;
233 clock-output-names = "sdhci_clk";
234 #clock-cells = <0>;
235 };
236
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]237 soc {
238 compatible = "simple-bus";
239 interrupt-parent = <&plic>;
240 #address-cells = <2>;
241 #size-cells = <2>;
242 dma-noncoherent;
243 ranges;
244
245 plic: interrupt-controller@ffd8000000 {
246 compatible = "thead,th1520-plic", "thead,c900-plic";
247 reg = <0xff 0xd8000000 0x0 0x01000000>;
248 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
249 <&cpu1_intc 11>, <&cpu1_intc 9>,
250 <&cpu2_intc 11>, <&cpu2_intc 9>,
251 <&cpu3_intc 11>, <&cpu3_intc 9>;
252 interrupt-controller;
253 #address-cells = <0>;
254 #interrupt-cells = <2>;
255 riscv,ndev = <240>;
256 };
257
258 clint: timer@ffdc000000 {
259 compatible = "thead,th1520-clint", "thead,c900-clint";
260 reg = <0xff 0xdc000000 0x0 0x00010000>;
261 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
262 <&cpu1_intc 3>, <&cpu1_intc 7>,
263 <&cpu2_intc 3>, <&cpu2_intc 7>,
264 <&cpu3_intc 3>, <&cpu3_intc 7>;
265 };
266
267 uart0: serial@ffe7014000 {
268 compatible = "snps,dw-apb-uart";
269 reg = <0xff 0xe7014000 0x0 0x100>;
270 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&uart_sclk>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
274 status = "disabled";
275 };
276
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]277 emmc: mmc@ffe7080000 {
278 compatible = "thead,th1520-dwcmshc";
279 reg = <0xff 0xe7080000 0x0 0x10000>;
280 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&sdhci_clk>;
282 clock-names = "core";
283 status = "disabled";
284 };
285
286 sdio0: mmc@ffe7090000 {
287 compatible = "thead,th1520-dwcmshc";
288 reg = <0xff 0xe7090000 0x0 0x10000>;
289 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&sdhci_clk>;
291 clock-names = "core";
292 status = "disabled";
293 };
294
295 sdio1: mmc@ffe70a0000 {
296 compatible = "thead,th1520-dwcmshc";
297 reg = <0xff 0xe70a0000 0x0 0x10000>;
298 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&sdhci_clk>;
300 clock-names = "core";
301 status = "disabled";
302 };
303
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]304 uart1: serial@ffe7f00000 {
305 compatible = "snps,dw-apb-uart";
306 reg = <0xff 0xe7f00000 0x0 0x100>;
307 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&uart_sclk>;
309 reg-shift = <2>;
310 reg-io-width = <4>;
311 status = "disabled";
312 };
313
314 uart3: serial@ffe7f04000 {
315 compatible = "snps,dw-apb-uart";
316 reg = <0xff 0xe7f04000 0x0 0x100>;
317 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&uart_sclk>;
319 reg-shift = <2>;
320 reg-io-width = <4>;
321 status = "disabled";
322 };
323
324 gpio2: gpio@ffe7f34000 {
325 compatible = "snps,dw-apb-gpio";
326 reg = <0xff 0xe7f34000 0x0 0x1000>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 portc: gpio-controller@0 {
331 compatible = "snps,dw-apb-gpio-port";
332 gpio-controller;
333 #gpio-cells = <2>;
334 ngpios = <32>;
335 reg = <0>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
339 };
340 };
341
342 gpio3: gpio@ffe7f38000 {
343 compatible = "snps,dw-apb-gpio";
344 reg = <0xff 0xe7f38000 0x0 0x1000>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347
348 portd: gpio-controller@0 {
349 compatible = "snps,dw-apb-gpio-port";
350 gpio-controller;
351 #gpio-cells = <2>;
352 ngpios = <32>;
353 reg = <0>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
357 };
358 };
359
360 gpio0: gpio@ffec005000 {
361 compatible = "snps,dw-apb-gpio";
362 reg = <0xff 0xec005000 0x0 0x1000>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 porta: gpio-controller@0 {
367 compatible = "snps,dw-apb-gpio-port";
368 gpio-controller;
369 #gpio-cells = <2>;
370 ngpios = <32>;
371 reg = <0>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
375 };
376 };
377
378 gpio1: gpio@ffec006000 {
379 compatible = "snps,dw-apb-gpio";
380 reg = <0xff 0xec006000 0x0 0x1000>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 portb: gpio-controller@0 {
385 compatible = "snps,dw-apb-gpio-port";
386 gpio-controller;
387 #gpio-cells = <2>;
388 ngpios = <32>;
389 reg = <0>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
392 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
393 };
394 };
395
396 uart2: serial@ffec010000 {
397 compatible = "snps,dw-apb-uart";
398 reg = <0xff 0xec010000 0x0 0x4000>;
399 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&uart_sclk>;
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 status = "disabled";
404 };
405
406 dmac0: dma-controller@ffefc00000 {
407 compatible = "snps,axi-dma-1.01a";
408 reg = <0xff 0xefc00000 0x0 0x1000>;
409 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&apb_clk>, <&apb_clk>;
411 clock-names = "core-clk", "cfgr-clk";
412 #dma-cells = <1>;
413 dma-channels = <4>;
414 snps,block-size = <65536 65536 65536 65536>;
415 snps,priority = <0 1 2 3>;
416 snps,dma-masters = <1>;
417 snps,data-width = <4>;
418 snps,axi-max-burst-len = <16>;
419 status = "disabled";
420 };
421
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]422 timer0: timer@ffefc32000 {
423 compatible = "snps,dw-apb-timer";
424 reg = <0xff 0xefc32000 0x0 0x14>;
425 clocks = <&apb_clk>;
426 clock-names = "timer";
427 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
428 status = "disabled";
429 };
430
431 timer1: timer@ffefc32014 {
432 compatible = "snps,dw-apb-timer";
433 reg = <0xff 0xefc32014 0x0 0x14>;
434 clocks = <&apb_clk>;
435 clock-names = "timer";
436 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
437 status = "disabled";
438 };
439
440 timer2: timer@ffefc32028 {
441 compatible = "snps,dw-apb-timer";
442 reg = <0xff 0xefc32028 0x0 0x14>;
443 clocks = <&apb_clk>;
444 clock-names = "timer";
445 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
446 status = "disabled";
447 };
448
449 timer3: timer@ffefc3203c {
450 compatible = "snps,dw-apb-timer";
451 reg = <0xff 0xefc3203c 0x0 0x14>;
452 clocks = <&apb_clk>;
453 clock-names = "timer";
454 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
455 status = "disabled";
456 };
457
458 uart4: serial@fff7f08000 {
459 compatible = "snps,dw-apb-uart";
460 reg = <0xff 0xf7f08000 0x0 0x4000>;
461 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&uart_sclk>;
463 reg-shift = <2>;
464 reg-io-width = <4>;
465 status = "disabled";
466 };
467
468 uart5: serial@fff7f0c000 {
469 compatible = "snps,dw-apb-uart";
470 reg = <0xff 0xf7f0c000 0x0 0x4000>;
471 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&uart_sclk>;
473 reg-shift = <2>;
474 reg-io-width = <4>;
475 status = "disabled";
476 };
477
478 timer4: timer@ffffc33000 {
479 compatible = "snps,dw-apb-timer";
480 reg = <0xff 0xffc33000 0x0 0x14>;
481 clocks = <&apb_clk>;
482 clock-names = "timer";
483 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
484 status = "disabled";
485 };
486
487 timer5: timer@ffffc33014 {
488 compatible = "snps,dw-apb-timer";
489 reg = <0xff 0xffc33014 0x0 0x14>;
490 clocks = <&apb_clk>;
491 clock-names = "timer";
492 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
493 status = "disabled";
494 };
495
496 timer6: timer@ffffc33028 {
497 compatible = "snps,dw-apb-timer";
498 reg = <0xff 0xffc33028 0x0 0x14>;
499 clocks = <&apb_clk>;
500 clock-names = "timer";
501 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
502 status = "disabled";
503 };
504
505 timer7: timer@ffffc3303c {
506 compatible = "snps,dw-apb-timer";
507 reg = <0xff 0xffc3303c 0x0 0x14>;
508 clocks = <&apb_clk>;
509 clock-names = "timer";
510 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
511 status = "disabled";
512 };
513
514 ao_gpio0: gpio@fffff41000 {
515 compatible = "snps,dw-apb-gpio";
516 reg = <0xff 0xfff41000 0x0 0x1000>;
517 #address-cells = <1>;
518 #size-cells = <0>;
519
520 porte: gpio-controller@0 {
521 compatible = "snps,dw-apb-gpio-port";
522 gpio-controller;
523 #gpio-cells = <2>;
524 ngpios = <32>;
525 reg = <0>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
529 };
530 };
531
532 ao_gpio1: gpio@fffff52000 {
533 compatible = "snps,dw-apb-gpio";
534 reg = <0xff 0xfff52000 0x0 0x1000>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 portf: gpio-controller@0 {
539 compatible = "snps,dw-apb-gpio-port";
540 gpio-controller;
541 #gpio-cells = <2>;
542 ngpios = <32>;
543 reg = <0>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
546 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
547 };
548 };
549 };
550};