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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / src / arm64 / rockchip / rk3588-turing-rk1.dtsi
blob: dbaa94ca69f47628a97d263684ad62cf746b407f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device tree definitions for the Turing RK1 SoM.
4 *
5 * Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com>
6 *
7 * Based on RK3588-EVB1 devicetree
8 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
9 */
10
11/dts-v1/;
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/pinctrl/rockchip.h>
14#include "rk3588.dtsi"
15
16/ {
17 compatible = "turing,rk1", "rockchip,rk3588";
18
19 aliases {
20 ethernet0 = &gmac1;
21 mmc0 = &sdhci;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]22 };
23
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
27 fan-supply = <&vcc5v0_sys>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pwm0m2_pins &fan_int>;
30 interrupt-parent = <&gpio0>;
31 interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
32 pwms = <&pwm0 0 50000 0>;
33 #cooling-cells = <2>;
34 };
35
36 vcc3v3_pcie30: vcc3v3-pcie30-regulator {
37 compatible = "regulator-fixed";
38 regulator-name = "vcc3v3_pcie30";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 enable-active-high;
42 gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&vcc3v3_pcie30_en>;
45 startup-delay-us = <5000>;
46 };
47
48 vcc5v0_sys: vcc5v0-sys-regulator {
49 compatible = "regulator-fixed";
50 regulator-name = "vcc5v0_sys";
51 regulator-always-on;
52 regulator-boot-on;
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 };
56
57 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
58 compatible = "regulator-fixed";
59 regulator-name = "vcc_1v1_nldo_s3";
60 regulator-always-on;
61 regulator-boot-on;
62 regulator-min-microvolt = <1100000>;
63 regulator-max-microvolt = <1100000>;
64 vin-supply = <&vcc5v0_sys>;
65 };
66};
67
68&combphy2_psu {
69 status = "okay";
70};
71
72&cpu_b0 {
73 cpu-supply = <&vdd_cpu_big0_s0>;
74};
75
76&cpu_b1 {
77 cpu-supply = <&vdd_cpu_big0_s0>;
78};
79
80&cpu_b2 {
81 cpu-supply = <&vdd_cpu_big1_s0>;
82};
83
84&cpu_b3 {
85 cpu-supply = <&vdd_cpu_big1_s0>;
86};
87
88&cpu_l0 {
89 cpu-supply = <&vdd_cpu_lit_s0>;
90};
91
92&cpu_l1 {
93 cpu-supply = <&vdd_cpu_lit_s0>;
94};
95
96&cpu_l2 {
97 cpu-supply = <&vdd_cpu_lit_s0>;
98};
99
100&cpu_l3 {
101 cpu-supply = <&vdd_cpu_lit_s0>;
102};
103
104&gmac1 {
105 clock_in_out = "output";
106 phy-handle = <&rgmii_phy>;
107 phy-mode = "rgmii-rxid";
108 pinctrl-0 = <&gmac1_miim
109 &gmac1_tx_bus2
110 &gmac1_rx_bus2
111 &gmac1_rgmii_clk
112 &gmac1_rgmii_bus>;
113 pinctrl-names = "default";
114 rx_delay = <0x00>;
115 tx_delay = <0x43>;
116 status = "okay";
117};
118
119&i2c0 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&i2c0m2_xfer>;
122 status = "okay";
123
124 vdd_cpu_big0_s0: regulator@42 {
125 compatible = "rockchip,rk8602";
126 reg = <0x42>;
127 fcs,suspend-voltage-selector = <1>;
128 regulator-name = "vdd_cpu_big0_s0";
129 regulator-always-on;
130 regulator-boot-on;
131 regulator-min-microvolt = <550000>;
132 regulator-max-microvolt = <1050000>;
133 regulator-ramp-delay = <2300>;
134 vin-supply = <&vcc5v0_sys>;
135
136 regulator-state-mem {
137 regulator-off-in-suspend;
138 };
139 };
140
141 vdd_cpu_big1_s0: regulator@43 {
142 compatible = "rockchip,rk8603", "rockchip,rk8602";
143 reg = <0x43>;
144 fcs,suspend-voltage-selector = <1>;
145 regulator-name = "vdd_cpu_big1_s0";
146 regulator-always-on;
147 regulator-boot-on;
148 regulator-min-microvolt = <550000>;
149 regulator-max-microvolt = <1050000>;
150 regulator-ramp-delay = <2300>;
151 vin-supply = <&vcc5v0_sys>;
152
153 regulator-state-mem {
154 regulator-off-in-suspend;
155 };
156 };
157};
158
159&i2c1 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&i2c1m2_xfer>;
162 status = "okay";
163
164 vdd_npu_s0: regulator@42 {
165 compatible = "rockchip,rk8602";
166 reg = <0x42>;
167 fcs,suspend-voltage-selector = <1>;
168 regulator-name = "vdd_npu_s0";
169 regulator-always-on;
170 regulator-boot-on;
171 regulator-min-microvolt = <550000>;
172 regulator-max-microvolt = <950000>;
173 regulator-ramp-delay = <2300>;
174 vin-supply = <&vcc5v0_sys>;
175
176 regulator-state-mem {
177 regulator-off-in-suspend;
178 };
179 };
180};
181
182&i2c6 {
183 status = "okay";
184
185 hym8563: rtc@51 {
186 compatible = "haoyu,hym8563";
187 reg = <0x51>;
188 #clock-cells = <0>;
189 clock-output-names = "hym8563";
190 pinctrl-names = "default";
191 pinctrl-0 = <&hym8563_int>;
192 interrupt-parent = <&gpio0>;
193 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
194 wakeup-source;
195 };
196};
197
198&mdio1 {
199 rgmii_phy: ethernet-phy@1 {
200 /* RTL8211F */
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]201 compatible = "ethernet-phy-id001c.c916";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]202 reg = <0x1>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&rtl8211f_rst>;
205 reset-assert-us = <15000>;
206 reset-deassert-us = <50000>;
207 reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
208 };
209};
210
211&pcie2x1l1 {
212 linux,pci-domain = <1>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pcie2_reset>;
215 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
216 status = "okay";
217};
218
219&pcie30phy {
220 status = "okay";
221};
222
223&pcie3x4 {
224 linux,pci-domain = <0>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pcie3_reset>;
227 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
228 vpcie3v3-supply = <&vcc3v3_pcie30>;
229 status = "okay";
230};
231
232&pinctrl {
233 fan {
234 fan_int: fan-int {
235 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
236 };
237 };
238
239 hym8563 {
240 hym8563_int: hym8563-int {
241 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
242 };
243 };
244
245 pcie2 {
246 pcie2_reset: pcie2-reset {
247 rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
248 };
249 };
250
251 pcie3 {
252 pcie3_reset: pcie3-reset {
253 rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
254 };
255
256 vcc3v3_pcie30_en: pcie3-reg {
257 rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
258 };
259 };
260
261 rtl8211f {
262 rtl8211f_rst: rtl8211f-rst {
263 rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
264 };
265 };
266};
267
268&pwm0 {
269 status = "okay";
270};
271
272&sdhci {
273 bus-width = <8>;
274 no-sdio;
275 no-sd;
276 non-removable;
277 mmc-hs400-1_8v;
278 mmc-hs400-enhanced-strobe;
279 status = "okay";
280};
281
282&spi2 {
283 status = "okay";
284 pinctrl-names = "default";
285 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
286 num-cs = <1>;
287
288 pmic@0 {
289 compatible = "rockchip,rk806";
290 spi-max-frequency = <1000000>;
291 reg = <0x0>;
292
293 interrupt-parent = <&gpio0>;
294 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
295
296 pinctrl-names = "default";
297 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
298 <&rk806_dvs2_null>, <&rk806_dvs3_null>;
299
300 vcc1-supply = <&vcc5v0_sys>;
301 vcc2-supply = <&vcc5v0_sys>;
302 vcc3-supply = <&vcc5v0_sys>;
303 vcc4-supply = <&vcc5v0_sys>;
304 vcc5-supply = <&vcc5v0_sys>;
305 vcc6-supply = <&vcc5v0_sys>;
306 vcc7-supply = <&vcc5v0_sys>;
307 vcc8-supply = <&vcc5v0_sys>;
308 vcc9-supply = <&vcc5v0_sys>;
309 vcc10-supply = <&vcc5v0_sys>;
310 vcc11-supply = <&vcc_2v0_pldo_s3>;
311 vcc12-supply = <&vcc5v0_sys>;
312 vcc13-supply = <&vcc_1v1_nldo_s3>;
313 vcc14-supply = <&vcc_1v1_nldo_s3>;
314 vcca-supply = <&vcc5v0_sys>;
315
316 gpio-controller;
317 #gpio-cells = <2>;
318
319 rk806_dvs1_null: dvs1-null-pins {
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]320 pins = "gpio_pwrctrl1";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]321 function = "pin_fun0";
322 };
323
324 rk806_dvs2_null: dvs2-null-pins {
325 pins = "gpio_pwrctrl2";
326 function = "pin_fun0";
327 };
328
329 rk806_dvs3_null: dvs3-null-pins {
330 pins = "gpio_pwrctrl3";
331 function = "pin_fun0";
332 };
333
334 regulators {
335 vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
336 regulator-boot-on;
337 regulator-min-microvolt = <550000>;
338 regulator-max-microvolt = <950000>;
339 regulator-ramp-delay = <12500>;
340 regulator-name = "vdd_gpu_s0";
341 regulator-enable-ramp-delay = <400>;
342
343 regulator-state-mem {
344 regulator-off-in-suspend;
345 };
346 };
347
348 vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
349 regulator-always-on;
350 regulator-boot-on;
351 regulator-min-microvolt = <550000>;
352 regulator-max-microvolt = <950000>;
353 regulator-ramp-delay = <12500>;
354 regulator-name = "vdd_cpu_lit_s0";
355
356 regulator-state-mem {
357 regulator-off-in-suspend;
358 };
359 };
360
361 vdd_log_s0: dcdc-reg3 {
362 regulator-always-on;
363 regulator-boot-on;
364 regulator-min-microvolt = <675000>;
365 regulator-max-microvolt = <750000>;
366 regulator-ramp-delay = <12500>;
367 regulator-name = "vdd_log_s0";
368
369 regulator-state-mem {
370 regulator-off-in-suspend;
371 regulator-suspend-microvolt = <750000>;
372 };
373 };
374
375 vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
376 regulator-always-on;
377 regulator-boot-on;
378 regulator-min-microvolt = <550000>;
379 regulator-max-microvolt = <950000>;
380 regulator-ramp-delay = <12500>;
381 regulator-name = "vdd_vdenc_s0";
382
383 regulator-state-mem {
384 regulator-off-in-suspend;
385 };
386 };
387
388 vdd_ddr_s0: dcdc-reg5 {
389 regulator-always-on;
390 regulator-boot-on;
391 regulator-min-microvolt = <675000>;
392 regulator-max-microvolt = <900000>;
393 regulator-ramp-delay = <12500>;
394 regulator-name = "vdd_ddr_s0";
395
396 regulator-state-mem {
397 regulator-off-in-suspend;
398 regulator-suspend-microvolt = <850000>;
399 };
400 };
401
402 vdd2_ddr_s3: dcdc-reg6 {
403 regulator-always-on;
404 regulator-boot-on;
405 regulator-name = "vdd2_ddr_s3";
406
407 regulator-state-mem {
408 regulator-on-in-suspend;
409 };
410 };
411
412 vcc_2v0_pldo_s3: dcdc-reg7 {
413 regulator-always-on;
414 regulator-boot-on;
415 regulator-min-microvolt = <2000000>;
416 regulator-max-microvolt = <2000000>;
417 regulator-ramp-delay = <12500>;
418 regulator-name = "vdd_2v0_pldo_s3";
419
420 regulator-state-mem {
421 regulator-on-in-suspend;
422 regulator-suspend-microvolt = <2000000>;
423 };
424 };
425
426 vcc_3v3_s3: dcdc-reg8 {
427 regulator-always-on;
428 regulator-boot-on;
429 regulator-min-microvolt = <3300000>;
430 regulator-max-microvolt = <3300000>;
431 regulator-name = "vcc_3v3_s3";
432
433 regulator-state-mem {
434 regulator-on-in-suspend;
435 regulator-suspend-microvolt = <3300000>;
436 };
437 };
438
439 vddq_ddr_s0: dcdc-reg9 {
440 regulator-always-on;
441 regulator-boot-on;
442 regulator-name = "vddq_ddr_s0";
443
444 regulator-state-mem {
445 regulator-off-in-suspend;
446 };
447 };
448
449 vcc_1v8_s3: dcdc-reg10 {
450 regulator-always-on;
451 regulator-boot-on;
452 regulator-min-microvolt = <1800000>;
453 regulator-max-microvolt = <1800000>;
454 regulator-name = "vcc_1v8_s3";
455
456 regulator-state-mem {
457 regulator-on-in-suspend;
458 regulator-suspend-microvolt = <1800000>;
459 };
460 };
461
462 avcc_1v8_s0: pldo-reg1 {
463 regulator-always-on;
464 regulator-boot-on;
465 regulator-min-microvolt = <1800000>;
466 regulator-max-microvolt = <1800000>;
467 regulator-name = "avcc_1v8_s0";
468
469 regulator-state-mem {
470 regulator-off-in-suspend;
471 };
472 };
473
474 vcc_1v8_s0: pldo-reg2 {
475 regulator-always-on;
476 regulator-boot-on;
477 regulator-min-microvolt = <1800000>;
478 regulator-max-microvolt = <1800000>;
479 regulator-name = "vcc_1v8_s0";
480
481 regulator-state-mem {
482 regulator-off-in-suspend;
483 regulator-suspend-microvolt = <1800000>;
484 };
485 };
486
487 avdd_1v2_s0: pldo-reg3 {
488 regulator-always-on;
489 regulator-boot-on;
490 regulator-min-microvolt = <1200000>;
491 regulator-max-microvolt = <1200000>;
492 regulator-name = "avdd_1v2_s0";
493
494 regulator-state-mem {
495 regulator-off-in-suspend;
496 };
497 };
498
499 vcc_3v3_s0: pldo-reg4 {
500 regulator-always-on;
501 regulator-boot-on;
502 regulator-min-microvolt = <3300000>;
503 regulator-max-microvolt = <3300000>;
504 regulator-ramp-delay = <12500>;
505 regulator-name = "vcc_3v3_s0";
506
507 regulator-state-mem {
508 regulator-off-in-suspend;
509 };
510 };
511
512 vccio_sd_s0: pldo-reg5 {
513 regulator-always-on;
514 regulator-boot-on;
515 regulator-min-microvolt = <1800000>;
516 regulator-max-microvolt = <3300000>;
517 regulator-ramp-delay = <12500>;
518 regulator-name = "vccio_sd_s0";
519
520 regulator-state-mem {
521 regulator-off-in-suspend;
522 };
523 };
524
525 pldo6_s3: pldo-reg6 {
526 regulator-always-on;
527 regulator-boot-on;
528 regulator-min-microvolt = <1800000>;
529 regulator-max-microvolt = <1800000>;
530 regulator-name = "pldo6_s3";
531
532 regulator-state-mem {
533 regulator-on-in-suspend;
534 regulator-suspend-microvolt = <1800000>;
535 };
536 };
537
538 vdd_0v75_s3: nldo-reg1 {
539 regulator-always-on;
540 regulator-boot-on;
541 regulator-min-microvolt = <750000>;
542 regulator-max-microvolt = <750000>;
543 regulator-name = "vdd_0v75_s3";
544
545 regulator-state-mem {
546 regulator-on-in-suspend;
547 regulator-suspend-microvolt = <750000>;
548 };
549 };
550
551 vdd_ddr_pll_s0: nldo-reg2 {
552 regulator-always-on;
553 regulator-boot-on;
554 regulator-min-microvolt = <850000>;
555 regulator-max-microvolt = <850000>;
556 regulator-name = "vdd_ddr_pll_s0";
557
558 regulator-state-mem {
559 regulator-off-in-suspend;
560 regulator-suspend-microvolt = <850000>;
561 };
562 };
563
564 avdd_0v75_s0: nldo-reg3 {
565 regulator-always-on;
566 regulator-boot-on;
567 regulator-min-microvolt = <750000>;
568 regulator-max-microvolt = <750000>;
569 regulator-name = "avdd_0v75_s0";
570
571 regulator-state-mem {
572 regulator-off-in-suspend;
573 };
574 };
575
576 vdd_0v85_s0: nldo-reg4 {
577 regulator-always-on;
578 regulator-boot-on;
579 regulator-min-microvolt = <850000>;
580 regulator-max-microvolt = <850000>;
581 regulator-name = "vdd_0v85_s0";
582
583 regulator-state-mem {
584 regulator-off-in-suspend;
585 };
586 };
587
588 vdd_0v75_s0: nldo-reg5 {
589 regulator-always-on;
590 regulator-boot-on;
591 regulator-min-microvolt = <750000>;
592 regulator-max-microvolt = <750000>;
593 regulator-name = "vdd_0v75_s0";
594
595 regulator-state-mem {
596 regulator-off-in-suspend;
597 };
598 };
599 };
600 };
601};
602
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]603&tsadc {
604 status = "okay";
605};
606
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]607&uart2 {
608 pinctrl-0 = <&uart2m0_xfer>;
609 status = "okay";
610};
611
612&uart9 {
613 pinctrl-0 = <&uart9m0_xfer>;
614 status = "okay";
615};