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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / src / arm64 / freescale / imx93-9x9-qsb.dts
blob: 950dece83c24665c17944da052cf8808c0ecc6ed [file] [log] [blame]
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2/*
3 * Copyright 2024 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx93.dtsi"
10
11/ {
12 model = "NXP i.MX93 9x9 Quick Start Board";
13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";
14
15 chosen {
16 stdout-path = &lpuart1;
17 };
18
19 reserved-memory {
20 #address-cells = <2>;
21 #size-cells = <2>;
22 ranges;
23
24 linux,cma {
25 compatible = "shared-dma-pool";
26 reusable;
27 size = <0 0x10000000>;
28 linux,cma-default;
29 };
30
31 vdev0vring0: vdev0vring0@a4000000 {
32 reg = <0 0xa4000000 0 0x8000>;
33 no-map;
34 };
35
36 vdev0vring1: vdev0vring1@a4008000 {
37 reg = <0 0xa4008000 0 0x8000>;
38 no-map;
39 };
40
41 vdev1vring0: vdev1vring0@a4010000 {
42 reg = <0 0xa4010000 0 0x8000>;
43 no-map;
44 };
45
46 vdev1vring1: vdev1vring1@a4018000 {
47 reg = <0 0xa4018000 0 0x8000>;
48 no-map;
49 };
50
51 rsc_table: rsc-table@2021e000 {
52 reg = <0 0x2021e000 0 0x1000>;
53 no-map;
54 };
55
56 vdevbuffer: vdevbuffer@a4020000 {
57 compatible = "shared-dma-pool";
58 reg = <0 0xa4020000 0 0x100000>;
59 no-map;
60 };
61
62 };
63
64 reg_vref_1v8: regulator-adc-vref {
65 compatible = "regulator-fixed";
66 regulator-name = "VREF_1V8";
67 regulator-min-microvolt = <1800000>;
68 regulator-max-microvolt = <1800000>;
69 };
70
71 reg_rpi_3v3: regulator-rpi {
72 compatible = "regulator-fixed";
73 regulator-name = "VDD_RPI_3V3";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 };
79
80 reg_usdhc2_vmmc: regulator-usdhc2 {
81 compatible = "regulator-fixed";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
84 regulator-name = "VSD_3V3";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 off-on-delay-us = <12000>;
90 };
91};
92
93&adc1 {
94 vref-supply = <&reg_vref_1v8>;
95 status = "okay";
96};
97
98&cm33 {
99 mbox-names = "tx", "rx", "rxdb";
100 mboxes = <&mu1 0 1>,
101 <&mu1 1 1>,
102 <&mu1 3 1>;
103 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
104 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
105 status = "okay";
106};
107
108&eqos {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_eqos>;
111 phy-mode = "rgmii-id";
112 phy-handle = <&ethphy1>;
113 status = "okay";
114
115 mdio {
116 compatible = "snps,dwmac-mdio";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 clock-frequency = <5000000>;
120
121 ethphy1: ethernet-phy@1 {
122 compatible = "ethernet-phy-ieee802.3-c22";
123 reg = <1>;
124 eee-broken-1000t;
125 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
126 reset-assert-us = <10000>;
127 reset-deassert-us = <80000>;
128 realtek,clkout-disable;
129 };
130 };
131};
132
133&lpi2c1 {
134 clock-frequency = <400000>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_lpi2c1>;
137 status = "okay";
138
139 ptn5110: tcpc@50 {
140 compatible = "nxp,ptn5110", "tcpci";
141 reg = <0x50>;
142 interrupt-parent = <&gpio3>;
143 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
144
145 typec1_con: connector {
146 compatible = "usb-c-connector";
147 label = "USB-C";
148 power-role = "dual";
149 data-role = "dual";
150 try-power-role = "sink";
151 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
152 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
153 PDO_VAR(5000, 20000, 3000)>;
154 op-sink-microwatt = <15000000>;
155 self-powered;
156
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 port@0 {
162 reg = <0>;
163
164 typec1_dr_sw: endpoint {
165 remote-endpoint = <&usb1_drd_sw>;
166 };
167 };
168 };
169 };
170 };
171
172 rtc@53 {
173 compatible = "nxp,pcf2131";
174 reg = <0x53>;
175 interrupt-parent = <&pcal6524>;
176 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
177 };
178};
179
180&lpi2c2 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 clock-frequency = <400000>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_lpi2c2>;
186 status = "okay";
187
188 pcal6524: gpio@22 {
189 compatible = "nxp,pcal6524";
190 reg = <0x22>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 interrupt-parent = <&gpio3>;
196 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_pcal6524>;
199 };
200
201 pmic@25 {
202 compatible = "nxp,pca9451a";
203 reg = <0x25>;
204 interrupt-parent = <&pcal6524>;
205 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
206
207 regulators {
208 buck1: BUCK1 {
209 regulator-name = "BUCK1";
210 regulator-min-microvolt = <650000>;
211 regulator-max-microvolt = <2237500>;
212 regulator-boot-on;
213 regulator-always-on;
214 regulator-ramp-delay = <3125>;
215 };
216
217 buck2: BUCK2 {
218 regulator-name = "BUCK2";
219 regulator-min-microvolt = <600000>;
220 regulator-max-microvolt = <2187500>;
221 regulator-boot-on;
222 regulator-always-on;
223 regulator-ramp-delay = <3125>;
224 };
225
226 buck4: BUCK4{
227 regulator-name = "BUCK4";
228 regulator-min-microvolt = <600000>;
229 regulator-max-microvolt = <3400000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 buck5: BUCK5{
235 regulator-name = "BUCK5";
236 regulator-min-microvolt = <600000>;
237 regulator-max-microvolt = <3400000>;
238 regulator-boot-on;
239 regulator-always-on;
240 };
241
242 buck6: BUCK6 {
243 regulator-name = "BUCK6";
244 regulator-min-microvolt = <600000>;
245 regulator-max-microvolt = <3400000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 ldo1: LDO1 {
251 regulator-name = "LDO1";
252 regulator-min-microvolt = <1600000>;
253 regulator-max-microvolt = <3300000>;
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 ldo4: LDO4 {
259 regulator-name = "LDO4";
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-boot-on;
263 regulator-always-on;
264 };
265
266 ldo5: LDO5 {
267 regulator-name = "LDO5";
268 regulator-min-microvolt = <1800000>;
269 regulator-max-microvolt = <3300000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273 };
274 };
275};
276
277&lpuart1 { /* console */
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_uart1>;
280 status = "okay";
281};
282
283&mu1 {
284 status = "okay";
285};
286
287&mu2 {
288 status = "okay";
289};
290
291&usbotg1 {
292 dr_mode = "otg";
293 hnp-disable;
294 srp-disable;
295 adp-disable;
296 usb-role-switch;
297 disable-over-current;
298 samsung,picophy-pre-emp-curr-control = <3>;
299 samsung,picophy-dc-vol-level-adjust = <7>;
300 status = "okay";
301
302 port {
303 usb1_drd_sw: endpoint {
304 remote-endpoint = <&typec1_dr_sw>;
305 };
306 };
307};
308
309&usdhc1 {
310 pinctrl-names = "default", "state_100mhz", "state_200mhz";
311 pinctrl-0 = <&pinctrl_usdhc1>;
312 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
313 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
314 bus-width = <8>;
315 non-removable;
316 status = "okay";
317};
318
319&usdhc2 {
320 pinctrl-names = "default", "state_100mhz", "state_200mhz";
321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
322 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
323 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
324 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
325 vmmc-supply = <&reg_usdhc2_vmmc>;
326 bus-width = <4>;
327 no-mmc;
328 status = "okay";
329};
330
331&wdog3 {
332 status = "okay";
333};
334
335&iomuxc {
336 pinctrl_eqos: eqosgrp {
337 fsl,pins = <
338 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
339 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
340 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
341 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
342 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
343 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
344 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
345 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
346 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
347 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
348 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
349 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
350 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
351 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
352 >;
353 };
354
355 pinctrl_lpi2c1: lpi2c1grp {
356 fsl,pins = <
357 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
358 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
359 >;
360 };
361
362 pinctrl_lpi2c2: lpi2c2grp {
363 fsl,pins = <
364 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
365 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
366 >;
367 };
368
369 pinctrl_pcal6524: pcal6524grp {
370 fsl,pins = <
371 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
372 >;
373 };
374
375 pinctrl_uart1: uart1grp {
376 fsl,pins = <
377 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
378 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
379 >;
380 };
381
382 pinctrl_uart5: uart5grp {
383 fsl,pins = <
384 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
385 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
386 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
387 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
388 >;
389 };
390
391 /* need to config the SION for data and cmd pad, refer to ERR052021 */
392 pinctrl_usdhc1: usdhc1grp {
393 fsl,pins = <
394 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
395 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
396 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
397 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
398 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
399 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
400 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
401 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
402 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
403 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
404 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
405 >;
406 };
407
408 /* need to config the SION for data and cmd pad, refer to ERR052021 */
409 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
410 fsl,pins = <
411 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
412 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
413 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
414 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
415 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
416 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
417 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
418 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
419 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
420 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
421 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
422 >;
423 };
424
425 /* need to config the SION for data and cmd pad, refer to ERR052021 */
426 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
427 fsl,pins = <
428 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
429 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
430 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
431 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
432 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
433 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
434 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
435 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
436 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
437 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
438 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
439 >;
440 };
441
442 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
443 fsl,pins = <
444 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
445 >;
446 };
447
448 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
449 fsl,pins = <
450 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
451 >;
452 };
453
454 /* need to config the SION for data and cmd pad, refer to ERR052021 */
455 pinctrl_usdhc2: usdhc2grp {
456 fsl,pins = <
457 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
458 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
459 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
460 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
461 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
462 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
463 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
464 >;
465 };
466
467 /* need to config the SION for data and cmd pad, refer to ERR052021 */
468 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
469 fsl,pins = <
470 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
471 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
472 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
473 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
474 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
475 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
476 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
477 >;
478 };
479
480 /* need to config the SION for data and cmd pad, refer to ERR052021 */
481 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
482 fsl,pins = <
483 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
484 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
485 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
486 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
487 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
488 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
489 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
490 >;
491 };
492};