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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / src / arm / ti / omap / am335x-pdu001.dts
blob: 17574d0d05259ebb785e554300adb9b9abb724b9 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * pdu001.dts
3 *
4 * EETS GmbH PDU001 board device tree file
5 *
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]6 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]7 *
8 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13/dts-v1/;
14
15#include "am33xx.dtsi"
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/leds/leds-pca9532.h>
18
19/ {
20 model = "EETS,PDU001";
21 compatible = "ti,am33xx";
22
23 chosen {
24 stdout-path = &uart3;
25 };
26
27 cpus {
28 cpu@0 {
29 cpu0-supply = <&vdd1_reg>;
30 };
31 };
32
33 memory {
34 device_type = "memory";
35 reg = <0x80000000 0x10000000>; /* 256 MB */
36 };
37
38 vbat: fixedregulator@0 {
39 compatible = "regulator-fixed";
40 regulator-name = "vbat";
41 regulator-min-microvolt = <3600000>;
42 regulator-max-microvolt = <3600000>;
43 regulator-boot-on;
44 };
45
46 lis3_reg: fixedregulator@1 {
47 compatible = "regulator-fixed";
48 regulator-name = "lis3_reg";
49 regulator-boot-on;
50 };
51
52 panel {
53 compatible = "ti,tilcdc,panel";
54 status = "okay";
55 pinctrl-names = "default";
56 pinctrl-0 = <&lcd_pins_s0>;
57 panel-info {
58 ac-bias = <255>;
59 ac-bias-intrpt = <0>;
60 dma-burst-sz = <16>;
61 bpp = <16>;
62 fdd = <0x80>;
63 sync-edge = <0>;
64 sync-ctrl = <1>;
65 raster-order = <0>;
66 fifo-th = <0>;
67 };
68
69 display-timings {
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]70 timing-240x320p16 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]71 clock-frequency = <6500000>;
72 hactive = <240>;
73 vactive = <320>;
74 hfront-porch = <6>;
75 hback-porch = <6>;
76 hsync-len = <1>;
77 vback-porch = <6>;
78 vfront-porch = <6>;
79 vsync-len = <1>;
80 hsync-active = <0>;
81 vsync-active = <0>;
82 pixelclk-active = <1>;
83 de-active = <0>;
84 };
85 };
86 };
87};
88
89&am33xx_pinmux {
90 pinctrl-names = "default";
91 pinctrl-0 = <&clkout2_pin>;
92
93 i2c0_pins: i2c0-pins {
94 pinctrl-single,pins = <
95 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
96 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
97 >;
98 };
99
100 i2c1_pins: i2c1-pins {
101 pinctrl-single,pins = <
102 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
103 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
104 >;
105 };
106
107 i2c2_pins: i2c2-pins {
108 pinctrl-single,pins = <
109 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */
110 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */
111 >;
112 };
113
114 spi1_pins: spi1-pins {
115 pinctrl-single,pins = <
116 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
117 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
118 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
119 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
120 >;
121 };
122
123 uart0_pins: uart0-pins {
124 pinctrl-single,pins = <
125 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
126 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
127 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
128 >;
129 };
130
131 uart1_pins: uart1-pins {
132 pinctrl-single,pins = <
133 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
134 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
135 >;
136 };
137
138 uart3_pins: uart3-pins {
139 pinctrl-single,pins = <
140 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */
141 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
142 >;
143 };
144
145 clkout2_pin: clkout2-pins {
146 pinctrl-single,pins = <
147 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
148 >;
149 };
150
151 cpsw_default: cpsw-default-pins {
152 pinctrl-single,pins = <
153 /* Port 1 (emac0) */
154 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
155 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
156 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
157 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
158 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
159 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
160 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
161 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
162 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
163 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
164 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
165 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
166 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
167 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
168 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
169
170 /* Port 2 (emac1) */
171 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */
172 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
173 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */
174 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */
175 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */
176 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */
177 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */
178 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
179 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
180 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
181 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
182 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
183 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */
184 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */
185 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */
186 >;
187 };
188
189 davinci_mdio_default: davinci-mdio-default-pins {
190 pinctrl-single,pins = <
191 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
192 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
193 >;
194 };
195
196 mmc1_pins: mmc1-pins {
197 /* eMMC */
198 pinctrl-single,pins = <
199 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
200 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
201 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
202 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
203 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
204 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
205 >;
206 };
207
208 mmc2_pins: mmc2-pins {
209 /* SD cardcage */
210 pinctrl-single,pins = <
211 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
212 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
213 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
214 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
215 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
216 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
217 /* card change signal for frontpanel SD cardcage */
218 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
219 >;
220 };
221
222 lcd_pins_s0: lcd-s0-pins {
223 pinctrl-single,pins = <
224 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
225 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
226 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
227 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
228 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
229 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
230 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
231 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
232 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
233 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
234 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
235 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
236 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
237 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
238 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
239 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
240 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
241 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
242 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
243 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
244 >;
245 };
246
247 dcan0_pins: dcan0-pins {
248 pinctrl-single,pins = <
249 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */
250 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */
251 >;
252 };
253};
254
255&uart0 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&uart0_pins>;
258
259 rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
260 rs485-rts-active-high;
261 rs485-rts-delay = <0 0>;
262 linux,rs485-enabled-at-boot-time;
263
264 status = "okay";
265};
266
267&uart1 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&uart1_pins>;
270
271 status = "okay";
272};
273
274&uart3 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart3_pins>;
277
278 status = "okay";
279};
280
281&i2c0 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&i2c0_pins>;
284
285 status = "okay";
286 clock-frequency = <400000>;
287
288 tps: tps@2d {
289 reg = <0x2d>;
290 };
291
292 m2_eeprom: m2_eeprom@50 {
293 compatible = "atmel,24c256";
294 reg = <0x50>;
295 status = "okay";
296 };
297};
298
299&i2c1 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2c1_pins>;
302
303 status = "okay";
304 clock-frequency = <100000>;
305
306 board_24aa025e48: board_24aa025e48@50 {
307 compatible = "atmel,24c02";
308 reg = <0x50>;
309 };
310
311 backplane_24aa025e48: backplane_24aa025e48@53 {
312 compatible = "atmel,24c02";
313 reg = <0x53>;
314 };
315
316 pca9532: pca9532@60 {
317 compatible = "nxp,pca9532";
318 reg = <0x60>;
319 psc0 = <0x97>;
320 pwm0 = <0x80>;
321 psc1 = <0x97>;
322 pwm1 = <0x10>;
323
324 run.red@0 {
325 type = <PCA9532_TYPE_LED>;
326 };
327 run.green@1 {
328 type = <PCA9532_TYPE_LED>;
329 default-state = "on";
330 };
331 s2.red@2 {
332 type = <PCA9532_TYPE_LED>;
333 };
334 s2.green@3 {
335 type = <PCA9532_TYPE_LED>;
336 };
337 s1.yellow@4 {
338 type = <PCA9532_TYPE_LED>;
339 };
340 s1.green@5 {
341 type = <PCA9532_TYPE_LED>;
342 };
343 };
344
345 pca9530: pca9530@61 {
346 compatible = "nxp,pca9530";
347 reg = <0x61>;
348
349 tft-panel@0 {
350 type = <PCA9532_TYPE_LED>;
351 linux,default-trigger = "backlight";
352 default-state = "on";
353 };
354 };
355
356 mcp79400: rtc@6f {
357 compatible = "microchip,mcp7940x";
358 reg = <0x6f>;
359 };
360};
361
362&i2c2 {
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c2_pins>;
365
366 status = "okay";
367 clock-frequency = <100000>;
368};
369
370&spi1 {
371 pinctrl-names = "default";
372 pinctrl-0 = <&spi1_pins>;
373 ti,pindir-d0-out-d1-in;
374 status = "okay";
375
376 display-controller@0 {
377 compatible = "orisetech,otm3225a";
378 reg = <0>;
379 spi-max-frequency = <1000000>;
380 // SPI mode 3
381 spi-cpol;
382 spi-cpha;
383 status = "okay";
384 };
385};
386
387/*
388 * Disable soc's rtc as we have no VBAT for it. This makes the board
389 * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
390 */
391&rtc {
392 status = "disabled";
393};
394
395&lcdc {
396 status = "okay";
397};
398
399&elm {
400 status = "okay";
401};
402
403#include "../../tps65910.dtsi"
404
405&tps {
406 vcc1-supply = <&vbat>;
407 vcc2-supply = <&vbat>;
408 vcc3-supply = <&vbat>;
409 vcc4-supply = <&vbat>;
410 vcc5-supply = <&vbat>;
411 vcc6-supply = <&vbat>;
412 vcc7-supply = <&vbat>;
413 vccio-supply = <&vbat>;
414
415 regulators {
416 vrtc_reg: regulator@0 {
417 regulator-name = "ldo_vrtc";
418 regulator-always-on;
419 };
420
421 vio_reg: regulator@1 {
422 regulator-name = "buck_vdd_ddr";
423 regulator-always-on;
424 };
425
426 vdd1_reg: regulator@2 {
427 /* VDD_MPU voltage limits */
428 regulator-name = "buck_vdd_mpu";
429 regulator-min-microvolt = <912500>;
430 regulator-max-microvolt = <1312500>;
431 regulator-boot-on;
432 regulator-always-on;
433 };
434
435 vdd2_reg: regulator@3 {
436 /* VDD_CORE voltage limits */
437 regulator-name = "buck_vdd_core";
438 regulator-min-microvolt = <912500>;
439 regulator-max-microvolt = <1150000>;
440 regulator-boot-on;
441 regulator-always-on;
442 };
443
444 vdd3_reg: regulator@4 {
445 regulator-name = "boost_res";
446 regulator-always-on;
447 };
448
449 vdig1_reg: regulator@5 {
450 regulator-name = "ldo_vdig1";
451 regulator-always-on;
452 };
453
454 vdig2_reg: regulator@6 {
455 regulator-name = "ldo_vdig2";
456 regulator-always-on;
457 };
458
459 vpll_reg: regulator@7 {
460 regulator-name = "ldo_vpll";
461 regulator-always-on;
462 };
463
464 vdac_reg: regulator@8 {
465 regulator-name = "ldo_vdac";
466 regulator-always-on;
467 };
468
469 vaux1_reg: regulator@9 {
470 regulator-name = "ldo_vaux1";
471 regulator-always-on;
472 };
473
474 vaux2_reg: regulator@10 {
475 regulator-name = "ldo_vaux2";
476 regulator-always-on;
477 };
478
479 vaux33_reg: regulator@11 {
480 regulator-name = "ldo_vaux33";
481 regulator-always-on;
482 };
483
484 vmmc_reg: regulator@12 {
485 regulator-name = "ldo_vmmc";
486 regulator-min-microvolt = <1800000>;
487 regulator-max-microvolt = <3300000>;
488 regulator-always-on;
489 };
490
491 vbb_reg: regulator@13 {
492 regulator-name = "bat_vbb";
493 };
494 };
495};
496
497&mac_sw {
498 pinctrl-names = "default";
499 pinctrl-0 = <&cpsw_default>;
500 status = "okay";
501};
502
503&davinci_mdio_sw {
504 pinctrl-names = "default";
505 pinctrl-0 = <&davinci_mdio_default>;
506
507 ethphy0: ethernet-phy@0 {
508 reg = <0>;
509 };
510
511 ethphy1: ethernet-phy@1 {
512 reg = <1>;
513 };
514};
515
516&cpsw_port1 {
517 phy-handle = <&ethphy0>;
518 phy-mode = "mii";
519 ti,dual-emac-pvid = <1>;
520};
521
522&cpsw_port2 {
523 phy-handle = <&ethphy1>;
524 phy-mode = "mii";
525 ti,dual-emac-pvid = <2>;
526};
527
528&tscadc {
529 status = "okay";
530 tsc {
531 ti,wires = <4>;
532 ti,x-plate-resistance = <200>;
533 ti,coordinate-readouts = <5>;
534 ti,wire-config = <0x01 0x10 0x22 0x33>;
535 ti,charge-delay = <0x400>;
536 };
537
538 adc {
539 ti,adc-channels = <4 5 6 7>;
540 };
541};
542
543&mmc1 {
544 status = "okay";
545 vmmc-supply = <&vmmc_reg>;
546 bus-width = <4>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&mmc1_pins>;
549 non-removable;
550};
551
552&mmc2 {
553 status = "okay";
554 vmmc-supply = <&vmmc_reg>;
555 bus-width = <4>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&mmc2_pins>;
558 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
559};
560
561&sham {
562 status = "okay";
563};
564
565&aes {
566 status = "okay";
567};
568
569&dcan0 {
570 status = "okay";
571 pinctrl-names = "default";
572 pinctrl-0 = <&dcan0_pins>;
573};