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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / src / arm / st / stm32f746.dtsi
blob: 2537b3d47e6f0ce8e0830d8de08a88a71724a02b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "../armv7-m.dtsi"
44#include <dt-bindings/clock/stm32fx-clock.h>
45#include <dt-bindings/mfd/stm32f7-rcc.h>
46
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 clocks {
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
62 };
63
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
68 };
69
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
74 };
75 };
76
77 soc {
78 timers2: timers@40000000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "st,stm32-timers";
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
84 clock-names = "int";
85 status = "disabled";
86
87 pwm {
88 compatible = "st,stm32-pwm";
89 #pwm-cells = <3>;
90 status = "disabled";
91 };
92
93 timer@1 {
94 compatible = "st,stm32-timer-trigger";
95 reg = <1>;
96 status = "disabled";
97 };
98 };
99
100 timers3: timers@40000400 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "st,stm32-timers";
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
106 clock-names = "int";
107 status = "disabled";
108
109 pwm {
110 compatible = "st,stm32-pwm";
111 #pwm-cells = <3>;
112 status = "disabled";
113 };
114
115 timer@2 {
116 compatible = "st,stm32-timer-trigger";
117 reg = <2>;
118 status = "disabled";
119 };
120 };
121
122 timers4: timers@40000800 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
128 clock-names = "int";
129 status = "disabled";
130
131 pwm {
132 compatible = "st,stm32-pwm";
133 #pwm-cells = <3>;
134 status = "disabled";
135 };
136
137 timer@3 {
138 compatible = "st,stm32-timer-trigger";
139 reg = <3>;
140 status = "disabled";
141 };
142 };
143
144 timers5: timers@40000c00 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "st,stm32-timers";
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
150 clock-names = "int";
151 status = "disabled";
152
153 pwm {
154 compatible = "st,stm32-pwm";
155 #pwm-cells = <3>;
156 status = "disabled";
157 };
158
159 timer@4 {
160 compatible = "st,stm32-timer-trigger";
161 reg = <4>;
162 status = "disabled";
163 };
164 };
165
166 timers6: timers@40001000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "st,stm32-timers";
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
172 clock-names = "int";
173 status = "disabled";
174
175 timer@5 {
176 compatible = "st,stm32-timer-trigger";
177 reg = <5>;
178 status = "disabled";
179 };
180 };
181
182 timers7: timers@40001400 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "st,stm32-timers";
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
188 clock-names = "int";
189 status = "disabled";
190
191 timer@6 {
192 compatible = "st,stm32-timer-trigger";
193 reg = <6>;
194 status = "disabled";
195 };
196 };
197
198 timers12: timers@40001800 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "st,stm32-timers";
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
204 clock-names = "int";
205 status = "disabled";
206
207 pwm {
208 compatible = "st,stm32-pwm";
209 #pwm-cells = <3>;
210 status = "disabled";
211 };
212
213 timer@11 {
214 compatible = "st,stm32-timer-trigger";
215 reg = <11>;
216 status = "disabled";
217 };
218 };
219
220 timers13: timers@40001c00 {
221 compatible = "st,stm32-timers";
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
224 clock-names = "int";
225 status = "disabled";
226
227 pwm {
228 compatible = "st,stm32-pwm";
229 #pwm-cells = <3>;
230 status = "disabled";
231 };
232 };
233
234 timers14: timers@40002000 {
235 compatible = "st,stm32-timers";
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
238 clock-names = "int";
239 status = "disabled";
240
241 pwm {
242 compatible = "st,stm32-pwm";
243 #pwm-cells = <3>;
244 status = "disabled";
245 };
246 };
247
248 rtc: rtc@40002800 {
249 compatible = "st,stm32-rtc";
250 reg = <0x40002800 0x400>;
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
255 interrupts = <17 1>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
257 status = "disabled";
258 };
259
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]260 spi2: spi@40003800 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "st,stm32f7-spi";
264 reg = <0x40003800 0x400>;
265 interrupts = <36>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
267 status = "disabled";
268 };
269
270 spi3: spi@40003c00 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "st,stm32f7-spi";
274 reg = <0x40003c00 0x400>;
275 interrupts = <51>;
276 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
277 status = "disabled";
278 };
279
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]280 usart2: serial@40004400 {
281 compatible = "st,stm32f7-uart";
282 reg = <0x40004400 0x400>;
283 interrupts = <38>;
284 clocks = <&rcc 1 CLK_USART2>;
285 status = "disabled";
286 };
287
288 usart3: serial@40004800 {
289 compatible = "st,stm32f7-uart";
290 reg = <0x40004800 0x400>;
291 interrupts = <39>;
292 clocks = <&rcc 1 CLK_USART3>;
293 status = "disabled";
294 };
295
296 usart4: serial@40004c00 {
297 compatible = "st,stm32f7-uart";
298 reg = <0x40004c00 0x400>;
299 interrupts = <52>;
300 clocks = <&rcc 1 CLK_UART4>;
301 status = "disabled";
302 };
303
304 usart5: serial@40005000 {
305 compatible = "st,stm32f7-uart";
306 reg = <0x40005000 0x400>;
307 interrupts = <53>;
308 clocks = <&rcc 1 CLK_UART5>;
309 status = "disabled";
310 };
311
312 i2c1: i2c@40005400 {
313 compatible = "st,stm32f7-i2c";
314 reg = <0x40005400 0x400>;
315 interrupts = <31>,
316 <32>;
317 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
318 clocks = <&rcc 1 CLK_I2C1>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 status = "disabled";
322 };
323
324 i2c2: i2c@40005800 {
325 compatible = "st,stm32f7-i2c";
326 reg = <0x40005800 0x400>;
327 interrupts = <33>,
328 <34>;
329 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
330 clocks = <&rcc 1 CLK_I2C2>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 status = "disabled";
334 };
335
336 i2c3: i2c@40005c00 {
337 compatible = "st,stm32f7-i2c";
338 reg = <0x40005c00 0x400>;
339 interrupts = <72>,
340 <73>;
341 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
342 clocks = <&rcc 1 CLK_I2C3>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 i2c4: i2c@40006000 {
349 compatible = "st,stm32f7-i2c";
350 reg = <0x40006000 0x400>;
351 interrupts = <95>,
352 <96>;
353 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
354 clocks = <&rcc 1 CLK_I2C4>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 status = "disabled";
358 };
359
360 can1: can@40006400 {
361 compatible = "st,stm32f4-bxcan";
362 reg = <0x40006400 0x200>;
363 interrupts = <19>, <20>, <21>, <22>;
364 interrupt-names = "tx", "rx0", "rx1", "sce";
365 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
366 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
367 st,can-primary;
368 st,gcan = <&gcan1>;
369 status = "disabled";
370 };
371
372 gcan1: gcan@40006600 {
373 compatible = "st,stm32f4-gcan", "syscon";
374 reg = <0x40006600 0x200>;
375 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
376 };
377
378 can2: can@40006800 {
379 compatible = "st,stm32f4-bxcan";
380 reg = <0x40006800 0x200>;
381 interrupts = <63>, <64>, <65>, <66>;
382 interrupt-names = "tx", "rx0", "rx1", "sce";
383 resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
384 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
385 st,can-secondary;
386 st,gcan = <&gcan1>;
387 status = "disabled";
388 };
389
390 cec: cec@40006c00 {
391 compatible = "st,stm32-cec";
392 reg = <0x40006C00 0x400>;
393 interrupts = <94>;
394 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
395 clock-names = "cec", "hdmi-cec";
396 status = "disabled";
397 };
398
399 usart7: serial@40007800 {
400 compatible = "st,stm32f7-uart";
401 reg = <0x40007800 0x400>;
402 interrupts = <82>;
403 clocks = <&rcc 1 CLK_UART7>;
404 status = "disabled";
405 };
406
407 usart8: serial@40007c00 {
408 compatible = "st,stm32f7-uart";
409 reg = <0x40007c00 0x400>;
410 interrupts = <83>;
411 clocks = <&rcc 1 CLK_UART8>;
412 status = "disabled";
413 };
414
415 timers1: timers@40010000 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 compatible = "st,stm32-timers";
419 reg = <0x40010000 0x400>;
420 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
421 clock-names = "int";
422 status = "disabled";
423
424 pwm {
425 compatible = "st,stm32-pwm";
426 #pwm-cells = <3>;
427 status = "disabled";
428 };
429
430 timer@0 {
431 compatible = "st,stm32-timer-trigger";
432 reg = <0>;
433 status = "disabled";
434 };
435 };
436
437 timers8: timers@40010400 {
438 #address-cells = <1>;
439 #size-cells = <0>;
440 compatible = "st,stm32-timers";
441 reg = <0x40010400 0x400>;
442 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
443 clock-names = "int";
444 status = "disabled";
445
446 pwm {
447 compatible = "st,stm32-pwm";
448 #pwm-cells = <3>;
449 status = "disabled";
450 };
451
452 timer@7 {
453 compatible = "st,stm32-timer-trigger";
454 reg = <7>;
455 status = "disabled";
456 };
457 };
458
459 usart1: serial@40011000 {
460 compatible = "st,stm32f7-uart";
461 reg = <0x40011000 0x400>;
462 interrupts = <37>;
463 clocks = <&rcc 1 CLK_USART1>;
464 status = "disabled";
465 };
466
467 usart6: serial@40011400 {
468 compatible = "st,stm32f7-uart";
469 reg = <0x40011400 0x400>;
470 interrupts = <71>;
471 clocks = <&rcc 1 CLK_USART6>;
472 status = "disabled";
473 };
474
475 sdio2: mmc@40011c00 {
476 compatible = "arm,pl180", "arm,primecell";
477 arm,primecell-periphid = <0x00880180>;
478 reg = <0x40011c00 0x400>;
479 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
480 clock-names = "apb_pclk";
481 interrupts = <103>;
482 max-frequency = <48000000>;
483 status = "disabled";
484 };
485
486 sdio1: mmc@40012c00 {
487 compatible = "arm,pl180", "arm,primecell";
488 arm,primecell-periphid = <0x00880180>;
489 reg = <0x40012c00 0x400>;
490 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
491 clock-names = "apb_pclk";
492 interrupts = <49>;
493 max-frequency = <48000000>;
494 status = "disabled";
495 };
496
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]497 spi1: spi@40013000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "st,stm32f7-spi";
501 reg = <0x40013000 0x400>;
502 interrupts = <35>;
503 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
504 status = "disabled";
505 };
506
507 spi4: spi@40013400 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "st,stm32f7-spi";
511 reg = <0x40013400 0x400>;
512 interrupts = <84>;
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
514 status = "disabled";
515 };
516
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]517 syscfg: syscon@40013800 {
518 compatible = "st,stm32-syscfg", "syscon";
519 reg = <0x40013800 0x400>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]521 };
522
523 exti: interrupt-controller@40013c00 {
524 compatible = "st,stm32-exti";
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 reg = <0x40013C00 0x400>;
528 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
529 };
530
531 timers9: timers@40014000 {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "st,stm32-timers";
535 reg = <0x40014000 0x400>;
536 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
537 clock-names = "int";
538 status = "disabled";
539
540 pwm {
541 compatible = "st,stm32-pwm";
542 #pwm-cells = <3>;
543 status = "disabled";
544 };
545
546 timer@8 {
547 compatible = "st,stm32-timer-trigger";
548 reg = <8>;
549 status = "disabled";
550 };
551 };
552
553 timers10: timers@40014400 {
554 compatible = "st,stm32-timers";
555 reg = <0x40014400 0x400>;
556 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
557 clock-names = "int";
558 status = "disabled";
559
560 pwm {
561 compatible = "st,stm32-pwm";
562 #pwm-cells = <3>;
563 status = "disabled";
564 };
565 };
566
567 timers11: timers@40014800 {
568 compatible = "st,stm32-timers";
569 reg = <0x40014800 0x400>;
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
571 clock-names = "int";
572 status = "disabled";
573
574 pwm {
575 compatible = "st,stm32-pwm";
576 #pwm-cells = <3>;
577 status = "disabled";
578 };
579 };
580
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]581 spi5: spi@40015000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "st,stm32f7-spi";
585 reg = <0x40015000 0x400>;
586 interrupts = <85>;
587 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
588 status = "disabled";
589 };
590
591 spi6: spi@40015400 {
592 #address-cells = <1>;
593 #size-cells = <0>;
594 compatible = "st,stm32f7-spi";
595 reg = <0x40015400 0x400>;
596 interrupts = <86>;
597 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
598 status = "disabled";
599 };
600
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]601 ltdc: display-controller@40016800 {
602 compatible = "st,stm32-ltdc";
603 reg = <0x40016800 0x200>;
604 interrupts = <88>, <89>;
605 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
606 clocks = <&rcc 1 CLK_LCD>;
607 clock-names = "lcd";
608 status = "disabled";
609 };
610
611 pwrcfg: power-config@40007000 {
612 compatible = "st,stm32-power-config", "syscon";
613 reg = <0x40007000 0x400>;
614 };
615
616 crc: crc@40023000 {
617 compatible = "st,stm32f7-crc";
618 reg = <0x40023000 0x400>;
619 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
620 status = "disabled";
621 };
622
623 rcc: rcc@40023800 {
624 #reset-cells = <1>;
625 #clock-cells = <2>;
626 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
627 reg = <0x40023800 0x400>;
628 clocks = <&clk_hse>, <&clk_i2s_ckin>;
629 st,syscfg = <&pwrcfg>;
630 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
631 assigned-clock-rates = <1000000>;
632 };
633
634 dma1: dma-controller@40026000 {
635 compatible = "st,stm32-dma";
636 reg = <0x40026000 0x400>;
637 interrupts = <11>,
638 <12>,
639 <13>,
640 <14>,
641 <15>,
642 <16>,
643 <17>,
644 <47>;
645 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
646 #dma-cells = <4>;
647 status = "disabled";
648 };
649
650 dma2: dma-controller@40026400 {
651 compatible = "st,stm32-dma";
652 reg = <0x40026400 0x400>;
653 interrupts = <56>,
654 <57>,
655 <58>,
656 <59>,
657 <60>,
658 <68>,
659 <69>,
660 <70>;
661 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
662 #dma-cells = <4>;
663 st,mem2mem;
664 status = "disabled";
665 };
666
667 usbotg_hs: usb@40040000 {
668 compatible = "st,stm32f7-hsotg";
669 reg = <0x40040000 0x40000>;
670 interrupts = <77>;
671 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
672 clock-names = "otg";
673 g-rx-fifo-size = <256>;
674 g-np-tx-fifo-size = <32>;
675 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
676 status = "disabled";
677 };
678
679 usbotg_fs: usb@50000000 {
680 compatible = "st,stm32f4x9-fsotg";
681 reg = <0x50000000 0x40000>;
682 interrupts = <67>;
683 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
684 clock-names = "otg";
685 status = "disabled";
686 };
687 };
688};
689
690&systick {
691 clocks = <&rcc 1 0>;
692 status = "okay";
693};