| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Copyright 2012 Stefan Roese <sr@denx.de> |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <1>; |
| 9 | compatible = "st,spear600"; |
| 10 | |
| 11 | cpus { |
| 12 | #address-cells = <0>; |
| 13 | #size-cells = <0>; |
| 14 | |
| 15 | cpu { |
| 16 | compatible = "arm,arm926ej-s"; |
| 17 | device_type = "cpu"; |
| 18 | }; |
| 19 | }; |
| 20 | |
| 21 | memory { |
| 22 | device_type = "memory"; |
| 23 | reg = <0 0x40000000>; |
| 24 | }; |
| 25 | |
| 26 | ahb { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <1>; |
| 29 | compatible = "simple-bus"; |
| 30 | ranges = <0xd0000000 0xd0000000 0x30000000>; |
| 31 | |
| 32 | vic0: interrupt-controller@f1100000 { |
| 33 | compatible = "arm,pl190-vic"; |
| 34 | interrupt-controller; |
| 35 | reg = <0xf1100000 0x1000>; |
| 36 | #interrupt-cells = <1>; |
| 37 | }; |
| 38 | |
| 39 | vic1: interrupt-controller@f1000000 { |
| 40 | compatible = "arm,pl190-vic"; |
| 41 | interrupt-controller; |
| 42 | reg = <0xf1000000 0x1000>; |
| 43 | #interrupt-cells = <1>; |
| 44 | }; |
| 45 | |
| 46 | clcd: clcd@fc200000 { |
| 47 | compatible = "arm,pl110", "arm,primecell"; |
| 48 | reg = <0xfc200000 0x1000>; |
| 49 | interrupt-parent = <&vic1>; |
| 50 | interrupts = <13>; |
| 51 | status = "disabled"; |
| 52 | }; |
| 53 | |
| 54 | dmac: dma@fc400000 { |
| 55 | compatible = "arm,pl080", "arm,primecell"; |
| 56 | reg = <0xfc400000 0x1000>; |
| 57 | interrupt-parent = <&vic1>; |
| 58 | interrupts = <10>; |
| 59 | status = "disabled"; |
| 60 | }; |
| 61 | |
| 62 | gmac: ethernet@e0800000 { |
| 63 | compatible = "st,spear600-gmac"; |
| 64 | reg = <0xe0800000 0x8000>; |
| 65 | interrupt-parent = <&vic1>; |
| 66 | interrupts = <24 23>; |
| 67 | interrupt-names = "macirq", "eth_wake_irq"; |
| 68 | phy-mode = "gmii"; |
| 69 | status = "disabled"; |
| 70 | }; |
| 71 | |
| 72 | fsmc: flash@d1800000 { |
| 73 | compatible = "st,spear600-fsmc-nand"; |
| 74 | #address-cells = <1>; |
| 75 | #size-cells = <1>; |
| 76 | reg = <0xd1800000 0x1000 /* FSMC Register */ |
| 77 | 0xd2000000 0x0010 /* NAND Base DATA */ |
| 78 | 0xd2020000 0x0010 /* NAND Base ADDR */ |
| 79 | 0xd2010000 0x0010>; /* NAND Base CMD */ |
| 80 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; |
| 81 | status = "disabled"; |
| 82 | }; |
| 83 | |
| 84 | smi: flash@fc000000 { |
| 85 | compatible = "st,spear600-smi"; |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <1>; |
| 88 | reg = <0xfc000000 0x1000>; |
| 89 | interrupt-parent = <&vic1>; |
| 90 | interrupts = <12>; |
| 91 | status = "disabled"; |
| 92 | }; |
| 93 | |
| 94 | ehci_usb0: ehci@e1800000 { |
| 95 | compatible = "st,spear600-ehci", "usb-ehci"; |
| 96 | reg = <0xe1800000 0x1000>; |
| 97 | interrupt-parent = <&vic1>; |
| 98 | interrupts = <27>; |
| 99 | status = "disabled"; |
| 100 | }; |
| 101 | |
| 102 | ehci_usb1: ehci@e2000000 { |
| 103 | compatible = "st,spear600-ehci", "usb-ehci"; |
| 104 | reg = <0xe2000000 0x1000>; |
| 105 | interrupt-parent = <&vic1>; |
| 106 | interrupts = <29>; |
| 107 | status = "disabled"; |
| 108 | }; |
| 109 | |
| 110 | ohci_usb0: ohci@e1900000 { |
| 111 | compatible = "st,spear600-ohci", "usb-ohci"; |
| 112 | reg = <0xe1900000 0x1000>; |
| 113 | interrupt-parent = <&vic1>; |
| 114 | interrupts = <26>; |
| 115 | status = "disabled"; |
| 116 | }; |
| 117 | |
| 118 | ohci_usb1: ohci@e2100000 { |
| 119 | compatible = "st,spear600-ohci", "usb-ohci"; |
| 120 | reg = <0xe2100000 0x1000>; |
| 121 | interrupt-parent = <&vic1>; |
| 122 | interrupts = <28>; |
| 123 | status = "disabled"; |
| 124 | }; |
| 125 | |
| 126 | apb { |
| 127 | #address-cells = <1>; |
| 128 | #size-cells = <1>; |
| 129 | compatible = "simple-bus"; |
| 130 | ranges = <0xd0000000 0xd0000000 0x30000000>; |
| 131 | |
| 132 | uart0: serial@d0000000 { |
| 133 | compatible = "arm,pl011", "arm,primecell"; |
| 134 | reg = <0xd0000000 0x1000>; |
| 135 | interrupt-parent = <&vic0>; |
| 136 | interrupts = <24>; |
| 137 | status = "disabled"; |
| 138 | }; |
| 139 | |
| 140 | uart1: serial@d0080000 { |
| 141 | compatible = "arm,pl011", "arm,primecell"; |
| 142 | reg = <0xd0080000 0x1000>; |
| 143 | interrupt-parent = <&vic0>; |
| 144 | interrupts = <25>; |
| 145 | status = "disabled"; |
| 146 | }; |
| 147 | |
| 148 | /* local/cpu GPIO */ |
| 149 | gpio0: gpio@f0100000 { |
| 150 | #gpio-cells = <2>; |
| 151 | compatible = "arm,pl061", "arm,primecell"; |
| 152 | gpio-controller; |
| 153 | reg = <0xf0100000 0x1000>; |
| 154 | interrupt-parent = <&vic0>; |
| 155 | interrupts = <18>; |
| 156 | }; |
| 157 | |
| 158 | /* basic GPIO */ |
| 159 | gpio1: gpio@fc980000 { |
| 160 | #gpio-cells = <2>; |
| 161 | compatible = "arm,pl061", "arm,primecell"; |
| 162 | gpio-controller; |
| 163 | reg = <0xfc980000 0x1000>; |
| 164 | interrupt-parent = <&vic1>; |
| 165 | interrupts = <19>; |
| 166 | }; |
| 167 | |
| 168 | /* appl GPIO */ |
| 169 | gpio2: gpio@d8100000 { |
| 170 | #gpio-cells = <2>; |
| 171 | compatible = "arm,pl061", "arm,primecell"; |
| 172 | gpio-controller; |
| 173 | reg = <0xd8100000 0x1000>; |
| 174 | interrupt-parent = <&vic1>; |
| 175 | interrupts = <4>; |
| 176 | }; |
| 177 | |
| 178 | i2c: i2c@d0200000 { |
| 179 | #address-cells = <1>; |
| 180 | #size-cells = <0>; |
| 181 | compatible = "snps,designware-i2c"; |
| 182 | reg = <0xd0200000 0x1000>; |
| 183 | interrupt-parent = <&vic0>; |
| 184 | interrupts = <28>; |
| 185 | status = "disabled"; |
| 186 | }; |
| 187 | |
| 188 | rtc: rtc@fc900000 { |
| 189 | compatible = "st,spear600-rtc"; |
| 190 | reg = <0xfc900000 0x1000>; |
| 191 | interrupt-parent = <&vic0>; |
| 192 | interrupts = <10>; |
| 193 | status = "disabled"; |
| 194 | }; |
| 195 | |
| 196 | timer@f0000000 { |
| 197 | compatible = "st,spear-timer"; |
| 198 | reg = <0xf0000000 0x400>; |
| 199 | interrupt-parent = <&vic0>; |
| 200 | interrupts = <16>; |
| 201 | }; |
| 202 | |
| 203 | adc: adc@d820b000 { |
| 204 | compatible = "st,spear600-adc"; |
| 205 | reg = <0xd820b000 0x1000>; |
| 206 | interrupt-parent = <&vic1>; |
| 207 | interrupts = <6>; |
| 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | ssp1: spi@d0100000 { |
| 212 | compatible = "arm,pl022", "arm,primecell"; |
| 213 | reg = <0xd0100000 0x1000>; |
| 214 | #address-cells = <1>; |
| 215 | #size-cells = <0>; |
| 216 | interrupt-parent = <&vic0>; |
| 217 | interrupts = <26>; |
| 218 | status = "disabled"; |
| 219 | }; |
| 220 | |
| 221 | ssp2: spi@d0180000 { |
| 222 | compatible = "arm,pl022", "arm,primecell"; |
| 223 | reg = <0xd0180000 0x1000>; |
| 224 | #address-cells = <1>; |
| 225 | #size-cells = <0>; |
| 226 | interrupt-parent = <&vic0>; |
| 227 | interrupts = <27>; |
| 228 | status = "disabled"; |
| 229 | }; |
| 230 | |
| 231 | ssp3: spi@d8180000 { |
| 232 | compatible = "arm,pl022", "arm,primecell"; |
| 233 | reg = <0xd8180000 0x1000>; |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <0>; |
| 236 | interrupt-parent = <&vic1>; |
| 237 | interrupts = <5>; |
| 238 | status = "disabled"; |
| 239 | }; |
| 240 | }; |
| 241 | }; |
| 242 | }; |