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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2022 Renesas Electronics Corp.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
9
10maintainers:
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
13description:
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
16 with the Image Processing module, which provides the video capture capabilities.
17
18properties:
19 compatible:
20 items:
21 - enum:
Tom Rini6b642ac2024-10-01 12:20:28 -060022 - renesas,r9a07g043-csi2 # RZ/G2UL
Tom Rini53633a82024-02-29 12:33:36 -050023 - renesas,r9a07g044-csi2 # RZ/G2{L,LC}
24 - renesas,r9a07g054-csi2 # RZ/V2L
25 - const: renesas,rzg2l-csi2
26
27 reg:
28 maxItems: 1
29
30 interrupts:
31 maxItems: 1
32
33 clocks:
34 items:
35 - description: Internal clock for connecting CRU and MIPI
36 - description: CRU Main clock
37 - description: CRU Register access clock
38
39 clock-names:
40 items:
41 - const: system
42 - const: video
43 - const: apb
44
45 power-domains:
46 maxItems: 1
47
48 resets:
49 items:
50 - description: CRU_PRESETN reset terminal
51 - description: CRU_CMN_RSTB reset terminal
52
53 reset-names:
54 items:
55 - const: presetn
56 - const: cmn-rstb
57
58 ports:
59 $ref: /schemas/graph.yaml#/properties/ports
60
61 properties:
62 port@0:
63 $ref: /schemas/graph.yaml#/$defs/port-base
64 unevaluatedProperties: false
65 description:
66 Input port node, single endpoint describing the CSI-2 transmitter.
67
68 properties:
69 endpoint:
70 $ref: video-interfaces.yaml#
71 unevaluatedProperties: false
72
73 properties:
74 data-lanes:
75 minItems: 1
76 maxItems: 4
77 items:
78 maximum: 4
79
80 required:
81 - clock-lanes
82 - data-lanes
83
84 port@1:
85 $ref: /schemas/graph.yaml#/properties/port
86 description:
87 Output port node, Image Processing block connected to the CSI-2 receiver.
88
89 required:
90 - port@0
91 - port@1
92
93required:
94 - compatible
95 - reg
96 - interrupts
97 - clocks
98 - clock-names
99 - power-domains
100 - resets
101 - reset-names
102 - ports
103
104additionalProperties: false
105
106examples:
107 - |
108 #include <dt-bindings/clock/r9a07g044-cpg.h>
109 #include <dt-bindings/interrupt-controller/arm-gic.h>
110
111 csi: csi@10830400 {
112 compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
113 reg = <0x10830400 0xfc00>;
114 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
116 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
117 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
118 clock-names = "system", "video", "apb";
119 power-domains = <&cpg>;
120 resets = <&cpg R9A07G044_CRU_PRESETN>,
121 <&cpg R9A07G044_CRU_CMN_RSTB>;
122 reset-names = "presetn", "cmn-rstb";
123
124 ports {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 port@0 {
129 reg = <0>;
130
131 csi2_in: endpoint {
132 clock-lanes = <0>;
133 data-lanes = <1 2>;
134 remote-endpoint = <&ov5645_ep>;
135 };
136 };
137
138 port@1 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 reg = <1>;
143
144 csi2cru: endpoint@0 {
145 reg = <0>;
146 remote-endpoint = <&crucsi2>;
147 };
148 };
149 };
150 };