| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek DSI Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Chun-Kuang Hu <chunkuang.hu@kernel.org> |
| 11 | - Philipp Zabel <p.zabel@pengutronix.de> |
| 12 | - Jitao Shi <jitao.shi@mediatek.com> |
| 13 | |
| 14 | description: | |
| 15 | The MediaTek DSI function block is a sink of the display subsystem and can |
| 16 | drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- |
| 17 | channel output. |
| 18 | |
| 19 | allOf: |
| 20 | - $ref: /schemas/display/dsi-controller.yaml# |
| 21 | |
| 22 | properties: |
| 23 | compatible: |
| 24 | oneOf: |
| 25 | - enum: |
| 26 | - mediatek,mt2701-dsi |
| 27 | - mediatek,mt7623-dsi |
| 28 | - mediatek,mt8167-dsi |
| 29 | - mediatek,mt8173-dsi |
| 30 | - mediatek,mt8183-dsi |
| 31 | - mediatek,mt8186-dsi |
| 32 | - mediatek,mt8188-dsi |
| 33 | - items: |
| 34 | - enum: |
| 35 | - mediatek,mt6795-dsi |
| 36 | - const: mediatek,mt8173-dsi |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 37 | - items: |
| 38 | - enum: |
| 39 | - mediatek,mt8195-dsi |
| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 40 | - mediatek,mt8365-dsi |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 41 | - const: mediatek,mt8183-dsi |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 42 | |
| 43 | reg: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | interrupts: |
| 47 | maxItems: 1 |
| 48 | |
| 49 | power-domains: |
| 50 | maxItems: 1 |
| 51 | |
| 52 | clocks: |
| 53 | items: |
| 54 | - description: Engine Clock |
| 55 | - description: Digital Clock |
| 56 | - description: HS Clock |
| 57 | |
| 58 | clock-names: |
| 59 | items: |
| 60 | - const: engine |
| 61 | - const: digital |
| 62 | - const: hs |
| 63 | |
| 64 | resets: |
| 65 | maxItems: 1 |
| 66 | |
| 67 | phys: |
| 68 | maxItems: 1 |
| 69 | |
| 70 | phy-names: |
| 71 | items: |
| 72 | - const: dphy |
| 73 | |
| 74 | port: |
| 75 | $ref: /schemas/graph.yaml#/properties/port |
| 76 | description: |
| 77 | Output port node. This port should be connected to the input |
| 78 | port of an attached DSI panel or DSI-to-eDP encoder chip. |
| 79 | |
| 80 | required: |
| 81 | - compatible |
| 82 | - reg |
| 83 | - interrupts |
| 84 | - power-domains |
| 85 | - clocks |
| 86 | - clock-names |
| 87 | - phys |
| 88 | - phy-names |
| 89 | - port |
| 90 | |
| 91 | unevaluatedProperties: false |
| 92 | |
| 93 | examples: |
| 94 | - | |
| 95 | #include <dt-bindings/clock/mt8183-clk.h> |
| 96 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 97 | #include <dt-bindings/interrupt-controller/irq.h> |
| 98 | #include <dt-bindings/power/mt8183-power.h> |
| 99 | #include <dt-bindings/phy/phy.h> |
| 100 | #include <dt-bindings/reset/mt8183-resets.h> |
| 101 | |
| 102 | soc { |
| 103 | #address-cells = <2>; |
| 104 | #size-cells = <2>; |
| 105 | |
| 106 | dsi0: dsi@14014000 { |
| 107 | compatible = "mediatek,mt8183-dsi"; |
| 108 | reg = <0 0x14014000 0 0x1000>; |
| 109 | interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; |
| 110 | power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; |
| 111 | clocks = <&mmsys CLK_MM_DSI0_MM>, |
| 112 | <&mmsys CLK_MM_DSI0_IF>, |
| 113 | <&mipi_tx0>; |
| 114 | clock-names = "engine", "digital", "hs"; |
| 115 | resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; |
| 116 | phys = <&mipi_tx0>; |
| 117 | phy-names = "dphy"; |
| 118 | port { |
| 119 | dsi0_out: endpoint { |
| 120 | remote-endpoint = <&panel_in>; |
| 121 | }; |
| 122 | }; |
| 123 | }; |
| 124 | }; |
| 125 | |
| 126 | ... |