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git01.mediatek.com / filogic / uboot / 97799bc45d4aeb35b75ddc3b0290e5e8f635f49e / . / dts / upstream / Bindings / clock / qcom,videocc.yaml
blob: 340c7e5cf98024dedad6d7db4fea10e9f8077419 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller
8
9maintainers:
10 - Taniya Das <quic_tdas@quicinc.com>
11
12description: |
13 Qualcomm video clock control module provides the clocks, resets and power
14 domains on Qualcomm SoCs.
15
16 See also::
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
20 include/dt-bindings/clock/qcom,videocc-sm8150.h
21 include/dt-bindings/clock/qcom,videocc-sm8250.h
22
23properties:
24 compatible:
25 enum:
26 - qcom,sc7180-videocc
27 - qcom,sc7280-videocc
28 - qcom,sdm845-videocc
29 - qcom,sm8150-videocc
30 - qcom,sm8250-videocc
31
32 clocks:
33 minItems: 1
34 maxItems: 3
35
36 clock-names:
37 minItems: 1
38 maxItems: 3
39
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]40 power-domains:
41 description:
42 A phandle and PM domain specifier for the MMCX power domain.
43 maxItems: 1
44
45 required-opps:
46 description:
47 A phandle to an OPP node describing required MMCX performance point.
48 maxItems: 1
49
50required:
51 - compatible
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]52 - clocks
53 - clock-names
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]54 - '#power-domain-cells'
55
56allOf:
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]57 - $ref: qcom,gcc.yaml#
58
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]59 - if:
60 properties:
61 compatible:
62 enum:
63 - qcom,sc7180-videocc
64 - qcom,sdm845-videocc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]65 then:
66 properties:
67 clocks:
68 items:
69 - description: Board XO source
70 clock-names:
71 items:
72 - const: bi_tcxo
73
74 - if:
75 properties:
76 compatible:
77 enum:
78 - qcom,sc7280-videocc
79 then:
80 properties:
81 clocks:
82 items:
83 - description: Board XO source
84 - description: Board active XO source
85 clock-names:
86 items:
87 - const: bi_tcxo
88 - const: bi_tcxo_ao
89
90 - if:
91 properties:
92 compatible:
93 enum:
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]94 - qcom,sm8150-videocc
95 then:
96 properties:
97 clocks:
98 items:
99 - description: AHB
100 - description: Board XO source
101 clock-names:
102 items:
103 - const: iface
104 - const: bi_tcxo
105
106 - if:
107 properties:
108 compatible:
109 enum:
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]110 - qcom,sm8250-videocc
111 then:
112 properties:
113 clocks:
114 items:
115 - description: AHB
116 - description: Board XO source
117 - description: Board active XO source
118 clock-names:
119 items:
120 - const: iface
121 - const: bi_tcxo
122 - const: bi_tcxo_ao
123
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]124unevaluatedProperties: false
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]125
126examples:
127 - |
128 #include <dt-bindings/clock/qcom,rpmh.h>
129 #include <dt-bindings/power/qcom,rpmhpd.h>
130 clock-controller@ab00000 {
131 compatible = "qcom,sdm845-videocc";
132 reg = <0x0ab00000 0x10000>;
133 clocks = <&rpmhcc RPMH_CXO_CLK>;
134 clock-names = "bi_tcxo";
135 #clock-cells = <1>;
136 #reset-cells = <1>;
137 #power-domain-cells = <1>;
138 power-domains = <&rpmhpd RPMHPD_MMCX>;
139 required-opps = <&rpmhpd_opp_low_svs>;
140 };
141...