Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | * |
| 5 | * Texas Instruments' K3 SD Host Controller Interface |
| 6 | */ |
| 7 | |
| 8 | #include <clk.h> |
| 9 | #include <common.h> |
| 10 | #include <dm.h> |
| 11 | #include <malloc.h> |
| 12 | #include <power-domain.h> |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 13 | #include <regmap.h> |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 14 | #include <sdhci.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 15 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 17 | #include <linux/err.h> |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 18 | |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 19 | /* CTL_CFG Registers */ |
| 20 | #define CTL_CFG_2 0x14 |
| 21 | |
| 22 | #define SLOTTYPE_MASK GENMASK(31, 30) |
| 23 | #define SLOTTYPE_EMBEDDED BIT(30) |
| 24 | |
| 25 | /* PHY Registers */ |
| 26 | #define PHY_CTRL1 0x100 |
| 27 | #define PHY_CTRL2 0x104 |
| 28 | #define PHY_CTRL3 0x108 |
| 29 | #define PHY_CTRL4 0x10C |
| 30 | #define PHY_CTRL5 0x110 |
| 31 | #define PHY_CTRL6 0x114 |
| 32 | #define PHY_STAT1 0x130 |
| 33 | #define PHY_STAT2 0x134 |
| 34 | |
| 35 | #define IOMUX_ENABLE_SHIFT 31 |
| 36 | #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) |
| 37 | #define OTAPDLYENA_SHIFT 20 |
| 38 | #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) |
| 39 | #define OTAPDLYSEL_SHIFT 12 |
| 40 | #define OTAPDLYSEL_MASK GENMASK(15, 12) |
| 41 | #define STRBSEL_SHIFT 24 |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 42 | #define STRBSEL_4BIT_MASK GENMASK(27, 24) |
| 43 | #define STRBSEL_8BIT_MASK GENMASK(31, 24) |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 44 | #define SEL50_SHIFT 8 |
| 45 | #define SEL50_MASK BIT(SEL50_SHIFT) |
| 46 | #define SEL100_SHIFT 9 |
| 47 | #define SEL100_MASK BIT(SEL100_SHIFT) |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 48 | #define FREQSEL_SHIFT 8 |
| 49 | #define FREQSEL_MASK GENMASK(10, 8) |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 50 | #define DLL_TRIM_ICP_SHIFT 4 |
| 51 | #define DLL_TRIM_ICP_MASK GENMASK(7, 4) |
| 52 | #define DR_TY_SHIFT 20 |
| 53 | #define DR_TY_MASK GENMASK(22, 20) |
| 54 | #define ENDLL_SHIFT 1 |
| 55 | #define ENDLL_MASK BIT(ENDLL_SHIFT) |
| 56 | #define DLLRDY_SHIFT 0 |
| 57 | #define DLLRDY_MASK BIT(DLLRDY_SHIFT) |
| 58 | #define PDB_SHIFT 0 |
| 59 | #define PDB_MASK BIT(PDB_SHIFT) |
| 60 | #define CALDONE_SHIFT 1 |
| 61 | #define CALDONE_MASK BIT(CALDONE_SHIFT) |
| 62 | #define RETRIM_SHIFT 17 |
| 63 | #define RETRIM_MASK BIT(RETRIM_SHIFT) |
| 64 | |
| 65 | #define DRIVER_STRENGTH_50_OHM 0x0 |
| 66 | #define DRIVER_STRENGTH_33_OHM 0x1 |
| 67 | #define DRIVER_STRENGTH_66_OHM 0x2 |
| 68 | #define DRIVER_STRENGTH_100_OHM 0x3 |
| 69 | #define DRIVER_STRENGTH_40_OHM 0x4 |
| 70 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 71 | #define AM654_SDHCI_MIN_FREQ 400000 |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 72 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 73 | struct am654_sdhci_plat { |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 74 | struct mmc_config cfg; |
| 75 | struct mmc mmc; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 76 | struct regmap *base; |
| 77 | bool non_removable; |
Faiz Abbas | 7101e12 | 2020-07-29 07:03:41 +0530 | [diff] [blame] | 78 | u32 otap_del_sel[MMC_MODES_END]; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 79 | u32 trm_icp; |
| 80 | u32 drv_strength; |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 81 | u32 strb_sel; |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 82 | u32 flags; |
| 83 | #define DLL_PRESENT (1 << 0) |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 84 | #define IOMUX_PRESENT (1 << 1) |
| 85 | #define FREQSEL_2_BIT (1 << 2) |
| 86 | #define STRBSEL_4_BIT (1 << 3) |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 87 | bool dll_on; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 88 | }; |
| 89 | |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 90 | struct timing_data { |
| 91 | const char *binding; |
| 92 | u32 capability; |
| 93 | }; |
| 94 | |
| 95 | static const struct timing_data td[] = { |
| 96 | [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0}, |
| 97 | [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)}, |
| 98 | [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)}, |
| 99 | [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)}, |
| 100 | [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)}, |
| 101 | [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)}, |
| 102 | [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)}, |
| 103 | [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)}, |
| 104 | [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)}, |
| 105 | [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)}, |
| 106 | [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)}, |
| 107 | }; |
| 108 | |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 109 | struct am654_driver_data { |
| 110 | const struct sdhci_ops *ops; |
| 111 | u32 flags; |
| 112 | }; |
| 113 | |
Faiz Abbas | 7eecee6 | 2019-06-11 00:43:41 +0530 | [diff] [blame] | 114 | static void am654_sdhci_set_control_reg(struct sdhci_host *host) |
| 115 | { |
| 116 | struct mmc *mmc = (struct mmc *)host->mmc; |
| 117 | u32 reg; |
| 118 | |
| 119 | if (IS_SD(host->mmc) && |
| 120 | mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { |
| 121 | reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 122 | reg |= SDHCI_CTRL_VDD_180; |
| 123 | sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); |
| 124 | } |
| 125 | |
| 126 | sdhci_set_uhs_timing(host); |
| 127 | } |
| 128 | |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 129 | static int am654_sdhci_set_ios_post(struct sdhci_host *host) |
| 130 | { |
| 131 | struct udevice *dev = host->mmc->dev; |
| 132 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
| 133 | unsigned int speed = host->mmc->clock; |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 134 | int sel50, sel100, freqsel; |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 135 | u32 otap_del_sel; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 136 | u32 mask, val; |
| 137 | int ret; |
| 138 | |
| 139 | /* Reset SD Clock Enable */ |
| 140 | val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 141 | val &= ~SDHCI_CLOCK_CARD_EN; |
| 142 | sdhci_writew(host, val, SDHCI_CLOCK_CONTROL); |
| 143 | |
| 144 | /* power off phy */ |
| 145 | if (plat->dll_on) { |
| 146 | regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0); |
| 147 | |
| 148 | plat->dll_on = false; |
| 149 | } |
| 150 | |
| 151 | /* restart clock */ |
| 152 | sdhci_set_clock(host->mmc, speed); |
| 153 | |
| 154 | /* switch phy back on */ |
| 155 | if (speed > AM654_SDHCI_MIN_FREQ) { |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 156 | otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode]; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 157 | mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; |
| 158 | val = (1 << OTAPDLYENA_SHIFT) | |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 159 | (otap_del_sel << OTAPDLYSEL_SHIFT); |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 160 | |
| 161 | /* Write to STRBSEL for HS400 speed mode */ |
| 162 | if (host->mmc->selected_mode == MMC_HS_400) { |
| 163 | if (plat->flags & STRBSEL_4_BIT) |
| 164 | mask |= STRBSEL_4BIT_MASK; |
| 165 | else |
| 166 | mask |= STRBSEL_8BIT_MASK; |
| 167 | |
| 168 | val |= plat->strb_sel << STRBSEL_SHIFT; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 169 | } |
| 170 | |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 171 | regmap_update_bits(plat->base, PHY_CTRL4, mask, val); |
| 172 | |
| 173 | if (plat->flags & FREQSEL_2_BIT) { |
| 174 | switch (speed) { |
| 175 | case 200000000: |
| 176 | sel50 = 0; |
| 177 | sel100 = 0; |
| 178 | break; |
| 179 | case 100000000: |
| 180 | sel50 = 0; |
| 181 | sel100 = 1; |
| 182 | break; |
| 183 | default: |
| 184 | sel50 = 1; |
| 185 | sel100 = 0; |
| 186 | } |
| 187 | |
| 188 | /* Configure PHY DLL frequency */ |
| 189 | mask = SEL50_MASK | SEL100_MASK; |
| 190 | val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); |
| 191 | regmap_update_bits(plat->base, PHY_CTRL5, mask, val); |
| 192 | } else { |
| 193 | switch (speed) { |
| 194 | case 200000000: |
| 195 | freqsel = 0x0; |
| 196 | break; |
| 197 | default: |
| 198 | freqsel = 0x4; |
| 199 | } |
| 200 | regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK, |
| 201 | freqsel << FREQSEL_SHIFT); |
| 202 | } |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 203 | |
| 204 | /* Enable DLL */ |
| 205 | regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, |
| 206 | 0x1 << ENDLL_SHIFT); |
| 207 | /* |
| 208 | * Poll for DLL ready. Use a one second timeout. |
| 209 | * Works in all experiments done so far |
| 210 | */ |
| 211 | ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, |
| 212 | val & DLLRDY_MASK, 1000, 1000000); |
| 213 | if (ret) |
| 214 | return ret; |
| 215 | |
| 216 | plat->dll_on = true; |
| 217 | } |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 222 | int am654_sdhci_init(struct am654_sdhci_plat *plat) |
| 223 | { |
| 224 | u32 ctl_cfg_2 = 0; |
| 225 | u32 mask, val; |
| 226 | int ret; |
| 227 | |
| 228 | /* Reset OTAP to default value */ |
| 229 | mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; |
| 230 | regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); |
| 231 | |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 232 | if (plat->flags & DLL_PRESENT) { |
| 233 | regmap_read(plat->base, PHY_STAT1, &val); |
| 234 | if (~val & CALDONE_MASK) { |
| 235 | /* Calibrate IO lines */ |
| 236 | regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK, |
| 237 | PDB_MASK); |
| 238 | ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, |
| 239 | val, val & CALDONE_MASK, |
| 240 | 1, 20); |
| 241 | if (ret) |
| 242 | return ret; |
| 243 | } |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 244 | |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 245 | /* Configure DLL TRIM */ |
| 246 | mask = DLL_TRIM_ICP_MASK; |
| 247 | val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 248 | |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 249 | /* Configure DLL driver strength */ |
| 250 | mask |= DR_TY_MASK; |
| 251 | val |= plat->drv_strength << DR_TY_SHIFT; |
| 252 | regmap_update_bits(plat->base, PHY_CTRL1, mask, val); |
| 253 | } |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 254 | |
| 255 | /* Enable pins by setting IO mux to 0 */ |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 256 | if (plat->flags & IOMUX_PRESENT) |
| 257 | regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 258 | |
| 259 | /* Set slot type based on SD or eMMC */ |
| 260 | if (plat->non_removable) |
| 261 | ctl_cfg_2 = SLOTTYPE_EMBEDDED; |
| 262 | |
| 263 | regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2); |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
Faiz Abbas | e4425cb | 2020-02-26 13:44:34 +0530 | [diff] [blame] | 268 | #define MAX_SDCD_DEBOUNCE_TIME 2000 |
| 269 | static int am654_sdhci_deferred_probe(struct sdhci_host *host) |
| 270 | { |
| 271 | struct udevice *dev = host->mmc->dev; |
| 272 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
| 273 | unsigned long start; |
| 274 | int val; |
| 275 | |
| 276 | /* |
| 277 | * The controller takes about 1 second to debounce the card detect line |
| 278 | * and doesn't let us power on until that time is up. Instead of waiting |
| 279 | * for 1 second at every stage, poll on the CARD_PRESENT bit upto a |
| 280 | * maximum of 2 seconds to be safe.. |
| 281 | */ |
| 282 | start = get_timer(0); |
| 283 | do { |
| 284 | if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME) |
| 285 | return -ENOMEDIUM; |
| 286 | |
| 287 | val = mmc_getcd(host->mmc); |
| 288 | } while (!val); |
| 289 | |
| 290 | am654_sdhci_init(plat); |
| 291 | |
| 292 | return sdhci_probe(dev); |
| 293 | } |
| 294 | |
| 295 | const struct sdhci_ops am654_sdhci_ops = { |
| 296 | .deferred_probe = am654_sdhci_deferred_probe, |
| 297 | .set_ios_post = &am654_sdhci_set_ios_post, |
| 298 | .set_control_reg = &am654_sdhci_set_control_reg, |
| 299 | }; |
| 300 | |
| 301 | const struct am654_driver_data am654_drv_data = { |
| 302 | .ops = &am654_sdhci_ops, |
| 303 | .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT, |
| 304 | }; |
| 305 | |
| 306 | const struct am654_driver_data j721e_8bit_drv_data = { |
| 307 | .ops = &am654_sdhci_ops, |
| 308 | .flags = DLL_PRESENT, |
| 309 | }; |
| 310 | |
| 311 | static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) |
| 312 | { |
| 313 | struct udevice *dev = host->mmc->dev; |
| 314 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
| 315 | u32 otap_del_sel, mask, val; |
| 316 | |
| 317 | otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode]; |
| 318 | mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; |
| 319 | val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); |
| 320 | regmap_update_bits(plat->base, PHY_CTRL4, mask, val); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | const struct sdhci_ops j721e_4bit_sdhci_ops = { |
| 326 | .deferred_probe = am654_sdhci_deferred_probe, |
| 327 | .set_ios_post = &j721e_4bit_sdhci_set_ios_post, |
| 328 | }; |
| 329 | |
| 330 | const struct am654_driver_data j721e_4bit_drv_data = { |
| 331 | .ops = &j721e_4bit_sdhci_ops, |
| 332 | .flags = IOMUX_PRESENT, |
| 333 | }; |
| 334 | |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 335 | static int sdhci_am654_get_otap_delay(struct udevice *dev, |
| 336 | struct mmc_config *cfg) |
| 337 | { |
| 338 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
| 339 | int ret; |
| 340 | int i; |
| 341 | |
| 342 | /* ti,otap-del-sel-legacy is mandatory */ |
| 343 | ret = dev_read_u32(dev, "ti,otap-del-sel-legacy", |
| 344 | &plat->otap_del_sel[0]); |
| 345 | if (ret) |
| 346 | return ret; |
| 347 | /* |
| 348 | * Remove the corresponding capability if an otap-del-sel |
| 349 | * value is not found |
| 350 | */ |
| 351 | for (i = MMC_HS; i <= MMC_HS_400; i++) { |
| 352 | ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]); |
| 353 | if (ret) { |
| 354 | dev_dbg(dev, "Couldn't find %s\n", td[i].binding); |
| 355 | /* |
| 356 | * Remove the corresponding capability |
| 357 | * if an otap-del-sel value is not found |
| 358 | */ |
| 359 | cfg->host_caps &= ~td[i].capability; |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | return 0; |
| 364 | } |
| 365 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 366 | static int am654_sdhci_probe(struct udevice *dev) |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 367 | { |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 368 | struct am654_driver_data *drv_data = |
| 369 | (struct am654_driver_data *)dev_get_driver_data(dev); |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 370 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 371 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 372 | struct sdhci_host *host = dev_get_priv(dev); |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 373 | struct mmc_config *cfg = &plat->cfg; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 374 | struct clk clk; |
| 375 | unsigned long clock; |
| 376 | int ret; |
| 377 | |
Faiz Abbas | dc2bcc2 | 2020-01-16 19:42:18 +0530 | [diff] [blame] | 378 | ret = clk_get_by_name(dev, "clk_xin", &clk); |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 379 | if (ret) { |
| 380 | dev_err(dev, "failed to get clock\n"); |
| 381 | return ret; |
| 382 | } |
| 383 | |
| 384 | clock = clk_get_rate(&clk); |
| 385 | if (IS_ERR_VALUE(clock)) { |
| 386 | dev_err(dev, "failed to get rate\n"); |
| 387 | return clock; |
| 388 | } |
| 389 | |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 390 | host->max_clk = clock; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 391 | host->mmc = &plat->mmc; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 392 | host->mmc->dev = dev; |
| 393 | ret = sdhci_setup_cfg(cfg, host, cfg->f_max, |
| 394 | AM654_SDHCI_MIN_FREQ); |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 395 | if (ret) |
| 396 | return ret; |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 397 | |
Faiz Abbas | c6eb9e7 | 2020-02-26 13:44:33 +0530 | [diff] [blame] | 398 | ret = sdhci_am654_get_otap_delay(dev, cfg); |
| 399 | if (ret) |
| 400 | return ret; |
| 401 | |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 402 | host->ops = drv_data->ops; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 403 | host->mmc->priv = host; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 404 | upriv->mmc = host->mmc; |
| 405 | |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 406 | regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1); |
| 407 | |
Faiz Abbas | e4425cb | 2020-02-26 13:44:34 +0530 | [diff] [blame] | 408 | return 0; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 409 | } |
| 410 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 411 | static int am654_sdhci_ofdata_to_platdata(struct udevice *dev) |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 412 | { |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 413 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 414 | struct sdhci_host *host = dev_get_priv(dev); |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 415 | struct mmc_config *cfg = &plat->cfg; |
| 416 | u32 drv_strength; |
| 417 | int ret; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 418 | |
| 419 | host->name = dev->name; |
| 420 | host->ioaddr = (void *)dev_read_addr(dev); |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 421 | plat->non_removable = dev_read_bool(dev, "non-removable"); |
| 422 | |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 423 | if (plat->flags & DLL_PRESENT) { |
| 424 | ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); |
| 425 | if (ret) |
| 426 | return ret; |
| 427 | |
| 428 | ret = dev_read_u32(dev, "ti,driver-strength-ohm", |
| 429 | &drv_strength); |
| 430 | if (ret) |
| 431 | return ret; |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 432 | |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 433 | switch (drv_strength) { |
| 434 | case 50: |
| 435 | plat->drv_strength = DRIVER_STRENGTH_50_OHM; |
| 436 | break; |
| 437 | case 33: |
| 438 | plat->drv_strength = DRIVER_STRENGTH_33_OHM; |
| 439 | break; |
| 440 | case 66: |
| 441 | plat->drv_strength = DRIVER_STRENGTH_66_OHM; |
| 442 | break; |
| 443 | case 100: |
| 444 | plat->drv_strength = DRIVER_STRENGTH_100_OHM; |
| 445 | break; |
| 446 | case 40: |
| 447 | plat->drv_strength = DRIVER_STRENGTH_40_OHM; |
| 448 | break; |
| 449 | default: |
| 450 | dev_err(dev, "Invalid driver strength\n"); |
| 451 | return -EINVAL; |
| 452 | } |
Faiz Abbas | e9aed58 | 2019-06-11 00:43:38 +0530 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | ret = mmc_of_parse(dev, cfg); |
| 456 | if (ret) |
| 457 | return ret; |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 458 | |
| 459 | return 0; |
| 460 | } |
| 461 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 462 | static int am654_sdhci_bind(struct udevice *dev) |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 463 | { |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 464 | struct am654_driver_data *drv_data = |
| 465 | (struct am654_driver_data *)dev_get_driver_data(dev); |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 466 | struct am654_sdhci_plat *plat = dev_get_platdata(dev); |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 467 | |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 468 | plat->flags = drv_data->flags; |
| 469 | |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 470 | return sdhci_bind(dev, &plat->mmc, &plat->cfg); |
| 471 | } |
| 472 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 473 | static const struct udevice_id am654_sdhci_ids[] = { |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 474 | { |
| 475 | .compatible = "ti,am654-sdhci-5.1", |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 476 | .data = (ulong)&am654_drv_data, |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 477 | }, |
| 478 | { |
| 479 | .compatible = "ti,j721e-sdhci-8bit", |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 480 | .data = (ulong)&j721e_8bit_drv_data, |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 481 | }, |
| 482 | { |
| 483 | .compatible = "ti,j721e-sdhci-4bit", |
Faiz Abbas | 8cc051e | 2020-01-16 19:42:19 +0530 | [diff] [blame] | 484 | .data = (ulong)&j721e_4bit_drv_data, |
Faiz Abbas | fd8be70 | 2019-06-13 10:29:51 +0530 | [diff] [blame] | 485 | }, |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 486 | { } |
| 487 | }; |
| 488 | |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 489 | U_BOOT_DRIVER(am654_sdhci_drv) = { |
| 490 | .name = "am654_sdhci", |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 491 | .id = UCLASS_MMC, |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 492 | .of_match = am654_sdhci_ids, |
| 493 | .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata, |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 494 | .ops = &sdhci_ops, |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 495 | .bind = am654_sdhci_bind, |
| 496 | .probe = am654_sdhci_probe, |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 497 | .priv_auto_alloc_size = sizeof(struct sdhci_host), |
Faiz Abbas | d8fb309 | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 498 | .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat), |
Lokesh Vutla | bc9979f | 2018-08-27 15:57:54 +0530 | [diff] [blame] | 499 | }; |