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wdenk5f495752004-02-26 23:46:20 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc824x.h>
29#include <asm/processor.h>
30#include <asm/io.h>
31#include <pci.h>
32#include <ide.h>
Ben Warren052a5ea2008-08-31 20:37:00 -070033#include <netdev.h>
Peter Tyser62948502008-11-03 09:30:59 -060034#include <timestamp.h>
wdenk5f495752004-02-26 23:46:20 +000035#include "piix_pci.h"
36#include "eXalion.h"
37
38int checkboard (void)
39{
40 ulong busfreq = get_bus_freq (0);
41 char buf[32];
42
43 printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
Peter Tyser62948502008-11-03 09:30:59 -060044 printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
wdenk5f495752004-02-26 23:46:20 +000045 printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq));
46
47 return 0;
48}
49
50int checkflash (void)
51{
52 printf ("checkflash\n");
53 flash_init ();
54 return (0);
55}
56
Becky Brucebd99ae72008-06-09 16:03:40 -050057phys_size_t initdram (int board_type)
wdenk5f495752004-02-26 23:46:20 +000058{
59 int i, cnt;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060 volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
wdenk5f495752004-02-26 23:46:20 +000061 volatile ulong *addr;
62 ulong save[32];
63 ulong val, ret = 0;
64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065 for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
wdenk5f495752004-02-26 23:46:20 +000066 cnt >>= 1) {
67 addr = (volatile ulong *) base + cnt;
68 save[i++] = *addr;
69 *addr = ~cnt;
70 }
71
72 addr = (volatile ulong *) base;
73 save[i] = *addr;
74 *addr = 0;
75
76 if (*addr != 0) {
77 *addr = save[i];
78 goto Done;
79 }
80
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081 for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
wdenk5f495752004-02-26 23:46:20 +000082 addr = (volatile ulong *) base + cnt;
83 val = *addr;
84 *addr = save[--i];
85 if (val != ~cnt) {
86 ulong new_bank0_end = cnt * sizeof (long) - 1;
87 ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
88 ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
89
90 mear1 = (mear1 & 0xFFFFFF00) |
91 ((new_bank0_end & MICR_ADDR_MASK) >>
92 MICR_ADDR_SHIFT);
93 emear1 = (emear1 & 0xFFFFFF00) |
94 ((new_bank0_end & MICR_ADDR_MASK) >>
95 MICR_EADDR_SHIFT);
96 mpc824x_mpc107_setreg (MEAR1, mear1);
97 mpc824x_mpc107_setreg (EMEAR1, emear1);
98
99 ret = cnt * sizeof (long);
100 goto Done;
101 }
102 }
103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104 ret = CONFIG_SYS_MAX_RAM_SIZE;
wdenk5f495752004-02-26 23:46:20 +0000105 Done:
106 return ret;
107}
108
109int misc_init_r (void)
110{
111 pci_dev_t bdf;
112 u32 val32;
113 u8 val8;
114
115 puts ("ISA: ");
116 bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
117 if (bdf == -1) {
118 puts ("Unable to find PIIX4 ISA bridge !\n");
119 hang ();
120 }
121
122 /* set device for normal ISA instead EIO */
123 pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
124 val32 |= 0x00000001;
125 pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
126 printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
127 PCI_DEV (bdf), PCI_FUNC (bdf));
128
129 puts ("ISA: ");
130 bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
131 if (bdf == -1) {
132 puts ("Unable to find PIIX4 IDE controller !\n");
133 hang ();
134 }
135
136 /* Init BMIBA register */
137 /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
138 /* val32 |= 0x1000; */
139 /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
140
141 /* Enable BUS master and IO access */
142 val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
143 pci_write_config_dword (bdf, PCI_COMMAND, val32);
144
145 /* Set latency */
146 pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
147 val8 = 0x40;
148 pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
149
150 /* Enable Primary ATA/IDE */
151 pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
152 /* val32 = 0xa307a307; */
153 val32 = 0x00008000;
154 pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
155
156
157 printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
158 PCI_DEV (bdf), PCI_FUNC (bdf));
159
160 /* Try to get FAT working... */
161 /* fat_register_read(ide_read); */
162
163
164 return (0);
165}
166
167/*
168 * Show/Init PCI devices on the specified bus number.
169 */
170
171void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
172{
173 unsigned char line;
174
175 switch (PCI_DEV (dev)) {
176 case 16:
177 line = PCI_INT_A;
178 break;
179 case 17:
180 line = PCI_INT_B;
181 break;
182 case 18:
183 line = PCI_INT_C;
184 break;
185 case 19:
186 line = PCI_INT_D;
187 break;
188#if defined (CONFIG_MPC8245)
189 case 20:
190 line = PCI_INT_A;
191 break;
192 case 21:
193 line = PCI_INT_B;
194 break;
195 case 22:
196 line = PCI_INT_NA;
197 break;
198#endif
199 default:
200 line = PCI_INT_A;
201 break;
202 }
203 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
204}
205
206
207/*
208 * Initialize PCI Devices, report devices found.
209 */
210#ifndef CONFIG_PCI_PNP
211#if defined (CONFIG_MPC8240)
212static struct pci_config_table pci_eXalion_config_table[] = {
213 {
214 /* Intel 82559ER ethernet controller */
215 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
216 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
217 PCI_ENET0_MEMADDR,
218 PCI_COMMAND_MEMORY |
219 PCI_COMMAND_MASTER}},
220 {
221 /* Intel 82371AB PIIX4 PCI to ISA bridge */
222 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
223 pci_cfgfunc_config_device, {0,
224 0,
225 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
226 {
227 /* Intel 82371AB PIIX4 IDE controller */
228 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
229 pci_cfgfunc_config_device, {0,
230 0,
231 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
232 {}
233};
234#elif defined (CONFIG_MPC8245)
235static struct pci_config_table pci_eXalion_config_table[] = {
236 {
237 /* Intel 82559ER ethernet controller */
238 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
239 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
240 PCI_ENET0_MEMADDR,
241 PCI_COMMAND_MEMORY |
242 PCI_COMMAND_MASTER}},
243 {
244 /* Intel 82559ER ethernet controller */
245 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
246 pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
247 PCI_ENET1_MEMADDR,
248 PCI_COMMAND_MEMORY |
249 PCI_COMMAND_MASTER}},
250 {
251 /* Broadcom BCM5690 Gigabit switch */
252 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
253 pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
254 PCI_ENET2_MEMADDR,
255 PCI_COMMAND_MEMORY |
256 PCI_COMMAND_MASTER}},
257 {
258 /* Broadcom BCM5690 Gigabit switch */
259 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
260 pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
261 PCI_ENET3_MEMADDR,
262 PCI_COMMAND_MEMORY |
263 PCI_COMMAND_MASTER}},
264 {
265 /* Intel 82371AB PIIX4 PCI to ISA bridge */
266 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
267 pci_cfgfunc_config_device, {0,
268 0,
269 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
270 {
271 /* Intel 82371AB PIIX4 IDE controller */
272 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
273 pci_cfgfunc_config_device, {0,
274 0,
275 PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
276 {}
277};
278#else
279#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
280#endif
281
282#endif /* #ifndef CONFIG_PCI_PNP */
283
284struct pci_controller hose = {
285#ifndef CONFIG_PCI_PNP
286 config_table:pci_eXalion_config_table,
287 fixup_irq:pci_eXalion_fixup_irq,
288#endif
289};
290
291void pci_init_board (void)
292{
293 pci_mpc824x_init (&hose);
294}
Ben Warren052a5ea2008-08-31 20:37:00 -0700295
296int board_eth_init(bd_t *bis)
297{
298 return pci_eth_init(bis);
299}