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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jaehoon Chung7cf73072012-10-15 19:10:29 +00002/*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung7cf73072012-10-15 19:10:29 +00005 */
6
7#ifndef __DWMMC_HW_H
8#define __DWMMC_HW_H
9
Simon Glass274e0b02020-05-10 11:39:56 -060010#include <asm/cache.h>
Jaehoon Chung7cf73072012-10-15 19:10:29 +000011#include <asm/io.h>
12#include <mmc.h>
13
14#define DWMCI_CTRL 0x000
15#define DWMCI_PWREN 0x004
16#define DWMCI_CLKDIV 0x008
17#define DWMCI_CLKSRC 0x00C
18#define DWMCI_CLKENA 0x010
19#define DWMCI_TMOUT 0x014
20#define DWMCI_CTYPE 0x018
21#define DWMCI_BLKSIZ 0x01C
22#define DWMCI_BYTCNT 0x020
23#define DWMCI_INTMASK 0x024
24#define DWMCI_CMDARG 0x028
25#define DWMCI_CMD 0x02C
26#define DWMCI_RESP0 0x030
27#define DWMCI_RESP1 0x034
28#define DWMCI_RESP2 0x038
29#define DWMCI_RESP3 0x03C
30#define DWMCI_MINTSTS 0x040
31#define DWMCI_RINTSTS 0x044
32#define DWMCI_STATUS 0x048
33#define DWMCI_FIFOTH 0x04C
34#define DWMCI_CDETECT 0x050
35#define DWMCI_WRTPRT 0x054
36#define DWMCI_GPIO 0x058
37#define DWMCI_TCMCNT 0x05C
38#define DWMCI_TBBCNT 0x060
39#define DWMCI_DEBNCE 0x064
40#define DWMCI_USRID 0x068
41#define DWMCI_VERID 0x06C
42#define DWMCI_HCON 0x070
43#define DWMCI_UHS_REG 0x074
44#define DWMCI_BMOD 0x080
45#define DWMCI_PLDMND 0x084
46#define DWMCI_DBADDR 0x088
47#define DWMCI_IDSTS 0x08C
48#define DWMCI_IDINTEN 0x090
49#define DWMCI_DSCADDR 0x094
50#define DWMCI_BUFADDR 0x098
51#define DWMCI_DATA 0x200
52
53/* Interrupt Mask register */
54#define DWMCI_INTMSK_ALL 0xffffffff
55#define DWMCI_INTMSK_RE (1 << 1)
56#define DWMCI_INTMSK_CDONE (1 << 2)
57#define DWMCI_INTMSK_DTO (1 << 3)
58#define DWMCI_INTMSK_TXDR (1 << 4)
59#define DWMCI_INTMSK_RXDR (1 << 5)
Marek Vasuta6d91992018-11-06 23:42:11 +010060#define DWMCI_INTMSK_RCRC (1 << 6)
Jaehoon Chung7cf73072012-10-15 19:10:29 +000061#define DWMCI_INTMSK_DCRC (1 << 7)
62#define DWMCI_INTMSK_RTO (1 << 8)
63#define DWMCI_INTMSK_DRTO (1 << 9)
64#define DWMCI_INTMSK_HTO (1 << 10)
65#define DWMCI_INTMSK_FRUN (1 << 11)
66#define DWMCI_INTMSK_HLE (1 << 12)
67#define DWMCI_INTMSK_SBE (1 << 13)
68#define DWMCI_INTMSK_ACD (1 << 14)
69#define DWMCI_INTMSK_EBE (1 << 15)
70
71/* Raw interrupt Regsiter */
72#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
73 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
74#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
75/* CTRL register */
76#define DWMCI_CTRL_RESET (1 << 0)
77#define DWMCI_CTRL_FIFO_RESET (1 << 1)
78#define DWMCI_CTRL_DMA_RESET (1 << 2)
79#define DWMCI_DMA_EN (1 << 5)
80#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
81#define DWMCI_IDMAC_EN (1 << 25)
82#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
83 DWMCI_CTRL_DMA_RESET)
84
85/* CMD register */
86#define DWMCI_CMD_RESP_EXP (1 << 6)
87#define DWMCI_CMD_RESP_LENGTH (1 << 7)
88#define DWMCI_CMD_CHECK_CRC (1 << 8)
89#define DWMCI_CMD_DATA_EXP (1 << 9)
90#define DWMCI_CMD_RW (1 << 10)
91#define DWMCI_CMD_SEND_STOP (1 << 12)
92#define DWMCI_CMD_ABORT_STOP (1 << 14)
93#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
94#define DWMCI_CMD_UPD_CLK (1 << 21)
95#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
96#define DWMCI_CMD_START (1 << 31)
97
98/* CLKENA register */
99#define DWMCI_CLKEN_ENABLE (1 << 0)
100#define DWMCI_CLKEN_LOW_PWR (1 << 16)
101
102/* Card-type registe */
103#define DWMCI_CTYPE_1BIT 0
104#define DWMCI_CTYPE_4BIT (1 << 0)
105#define DWMCI_CTYPE_8BIT (1 << 16)
106
107/* Status Register */
Heiko Stuebner46b7a4f2018-09-21 10:59:45 +0200108#define DWMCI_FIFO_EMPTY (1 << 2)
109#define DWMCI_FIFO_FULL (1 << 3)
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000110#define DWMCI_BUSY (1 << 9)
Jaehoon Chung6463b372016-07-28 14:26:24 +0900111#define DWMCI_FIFO_MASK 0x1fff
huang lin50b73752015-11-17 14:20:22 +0800112#define DWMCI_FIFO_SHIFT 17
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000113
114/* FIFOTH Register */
115#define MSIZE(x) ((x) << 28)
116#define RX_WMARK(x) ((x) << 16)
117#define TX_WMARK(x) (x)
Amard8501212013-04-27 11:42:55 +0530118#define RX_WMARK_SHIFT 16
119#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000120
121#define DWMCI_IDMAC_OWN (1 << 31)
122#define DWMCI_IDMAC_CH (1 << 4)
123#define DWMCI_IDMAC_FS (1 << 3)
124#define DWMCI_IDMAC_LD (1 << 2)
125
126/* Bus Mode Register */
127#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
128#define DWMCI_BMOD_IDMAC_FB (1 << 1)
129#define DWMCI_BMOD_IDMAC_EN (1 << 7)
130
Jaehoon Chunge8672942014-05-16 13:59:55 +0900131/* UHS register */
132#define DWMCI_DDR_MODE (1 << 16)
133
Ley Foon Tanb98e8922018-12-20 17:55:41 +0800134/* Internal IDMAC interrupt defines */
135#define DWMCI_IDINTEN_RI BIT(1)
136#define DWMCI_IDINTEN_TI BIT(0)
137
138#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \
139 DWMCI_IDINTEN_RI)
140
Rajeshwari Shinde70163092013-10-29 12:53:13 +0530141/* quirks */
142#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
143
Simon Glassc3588812015-06-23 15:38:52 -0600144/**
145 * struct dwmci_host - Information about a designware MMC host
146 *
147 * @name: Device name
148 * @ioaddr: Base I/O address of controller
149 * @quirks: Quick flags - see DWMCI_QUIRK_...
150 * @caps: Capabilities - see MMC_MODE_...
151 * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
152 * @div: Arbitrary clock divider value for use by controller
153 * @dev_index: Arbitrary device index for use by controller
154 * @dev_id: Arbitrary device ID for use by controller
155 * @buswidth: Bus width in bits (8 or 4)
156 * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
157 * @mmc: Pointer to generic MMC structure for this device
158 * @priv: Private pointer for use by controller
159 */
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000160struct dwmci_host {
Simon Glassc3588812015-06-23 15:38:52 -0600161 const char *name;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000162 void *ioaddr;
163 unsigned int quirks;
164 unsigned int caps;
165 unsigned int version;
166 unsigned int clock;
167 unsigned int bus_hz;
Jaehoon Chung62811102014-05-16 13:59:52 +0900168 unsigned int div;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000169 int dev_index;
Jaehoon Chung62811102014-05-16 13:59:52 +0900170 int dev_id;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000171 int buswidth;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000172 u32 fifoth_val;
173 struct mmc *mmc;
Jaehoon Chungbcb03eab2015-02-04 15:48:40 +0900174 void *priv;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000175
176 void (*clksel)(struct dwmci_host *host);
Jaehoon Chung42f81a82013-11-29 20:08:57 +0900177 void (*board_init)(struct dwmci_host *host);
Simon Glasseff76682015-08-30 16:55:15 -0600178
179 /**
180 * Get / set a particular MMC clock frequency
181 *
182 * This is used to request the current clock frequency of the clock
183 * that drives the DWMMC peripheral. The caller will then use this
184 * information to work out the divider it needs to achieve the
185 * required MMC bus clock frequency. If you want to handle the
186 * clock external to DWMMC, use @freq to select the frequency and
187 * return that value too. Then DWMMC will put itself in bypass mode.
188 *
189 * @host: DWMMC host
190 * @freq: Frequency the host is trying to achieve
191 */
192 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
Simon Glass82682542016-05-14 14:03:07 -0600193#ifndef CONFIG_BLK
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200194 struct mmc_config cfg;
Simon Glass82682542016-05-14 14:03:07 -0600195#endif
huang lin50b73752015-11-17 14:20:22 +0800196
197 /* use fifo mode to read and write data */
198 bool fifo_mode;
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000199};
200
201struct dwmci_idmac {
202 u32 flags;
203 u32 cnt;
204 u32 addr;
205 u32 next_addr;
Marek Vasutdfcc5052014-09-15 01:18:15 +0200206} __aligned(ARCH_DMA_MINALIGN);
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000207
208static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
209{
210 writel(val, host->ioaddr + reg);
211}
212
213static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
214{
215 writew(val, host->ioaddr + reg);
216}
217
218static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
219{
220 writeb(val, host->ioaddr + reg);
221}
222static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
223{
224 return readl(host->ioaddr + reg);
225}
226
227static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
228{
229 return readw(host->ioaddr + reg);
230}
231
232static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
233{
234 return readb(host->ioaddr + reg);
235}
236
Simon Glass558f94a2016-06-12 23:30:13 -0600237#ifdef CONFIG_BLK
238/**
239 * dwmci_setup_cfg() - Set up the configuration for DWMMC
240 *
241 * This is used to set up a DWMMC device when you are using CONFIG_BLK.
242 *
243 * This should be called from your MMC driver's probe() method once you have
244 * the information required.
245 *
246 * Generally your driver will have a platform data structure which holds both
247 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
248 * For example:
249 *
250 * struct rockchip_mmc_plat {
251 * struct mmc_config cfg;
252 * struct mmc mmc;
253 * };
254 *
255 * ...
256 *
257 * Inside U_BOOT_DRIVER():
258 * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
259 *
260 * To access platform data:
261 * struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
262 *
263 * See rockchip_dw_mmc.c for an example.
264 *
265 * @cfg: Configuration structure to fill in (generally &plat->mmc)
Jaehoon Chungbf819d02016-09-23 19:13:16 +0900266 * @host: DWMMC host
Jaehoon Chung9f5f0fe2016-06-28 15:52:20 +0900267 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
268 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
Simon Glass558f94a2016-06-12 23:30:13 -0600269 */
Jaehoon Chungbf819d02016-09-23 19:13:16 +0900270void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
271 u32 max_clk, u32 min_clk);
Simon Glass558f94a2016-06-12 23:30:13 -0600272
273/**
274 * dwmci_bind() - Set up a new MMC block device
275 *
276 * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
277 * It should be called from your driver's bind() method.
278 *
279 * See rockchip_dw_mmc.c for an example.
280 *
281 * @dev: Device to set up
282 * @mmc: Pointer to mmc structure (normally &plat->mmc)
283 * @cfg: Empty configuration structure (generally &plat->cfg). This is
284 * normally all zeroes at this point. The only purpose of passing
285 * this in is to set mmc->cfg to it.
286 * @return 0 if OK, -ve if the block device could not be created
287 */
Simon Glass82682542016-05-14 14:03:07 -0600288int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
289
Simon Glass558f94a2016-06-12 23:30:13 -0600290#else
291/**
292 * add_dwmci() - Add a new DWMMC interface
293 *
294 * This is used when you are not using CONFIG_BLK. Convert your driver over!
295 *
296 * @host: DWMMC host structure
Jaehoon Chung9f5f0fe2016-06-28 15:52:20 +0900297 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
298 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
Simon Glass558f94a2016-06-12 23:30:13 -0600299 * @return 0 if OK, -ve on error
300 */
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000301int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
Simon Glass558f94a2016-06-12 23:30:13 -0600302#endif /* !CONFIG_BLK */
303
Simon Glasseba48f92017-07-29 11:35:31 -0600304#ifdef CONFIG_DM_MMC
Simon Glassff5c1b72016-06-12 23:30:23 -0600305/* Export the operations to drivers */
Simon Glassff5c1b72016-06-12 23:30:23 -0600306int dwmci_probe(struct udevice *dev);
307extern const struct dm_mmc_ops dm_dwmci_ops;
308#endif
309
Jaehoon Chung7cf73072012-10-15 19:10:29 +0000310#endif /* __DWMMC_HW_H */