Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 2 | /* |
| 3 | * |
| 4 | * (C) Copyright 2000-2003 |
| 5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 6 | * |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 7 | * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 8 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 12 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame^] | 13 | #include <init.h> |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 14 | #include <watchdog.h> |
TsiChungLiew | 97401c3 | 2007-07-05 23:03:28 -0500 | [diff] [blame] | 15 | #include <asm/immap.h> |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 16 | #include <asm/io.h> |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 17 | |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 18 | #if defined(CONFIG_MCFFEC) |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 19 | #include <config.h> |
| 20 | #include <net.h> |
| 21 | #include <asm/fec.h> |
| 22 | #endif |
| 23 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 24 | #ifdef CONFIG_MCF5301x |
| 25 | void cpu_init_f(void) |
| 26 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 27 | scm1_t *scm1 = (scm1_t *) MMAP_SCM1; |
| 28 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| 29 | fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 30 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 31 | out_be32(&scm1->mpr, 0x77777777); |
| 32 | out_be32(&scm1->pacra, 0); |
| 33 | out_be32(&scm1->pacrb, 0); |
| 34 | out_be32(&scm1->pacrc, 0); |
| 35 | out_be32(&scm1->pacrd, 0); |
| 36 | out_be32(&scm1->pacre, 0); |
| 37 | out_be32(&scm1->pacrf, 0); |
| 38 | out_be32(&scm1->pacrg, 0); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 39 | |
| 40 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ |
| 41 | && defined(CONFIG_SYS_CS0_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 42 | setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); |
| 43 | out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); |
| 44 | out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); |
| 45 | out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 46 | #endif |
| 47 | |
| 48 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ |
| 49 | && defined(CONFIG_SYS_CS1_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 50 | setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); |
| 51 | out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); |
| 52 | out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); |
| 53 | out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 54 | #endif |
| 55 | |
| 56 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ |
| 57 | && defined(CONFIG_SYS_CS2_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 58 | out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); |
| 59 | out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); |
| 60 | out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 61 | #endif |
| 62 | |
| 63 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ |
| 64 | && defined(CONFIG_SYS_CS3_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 65 | out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); |
| 66 | out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); |
| 67 | out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 68 | #endif |
| 69 | |
| 70 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ |
| 71 | && defined(CONFIG_SYS_CS4_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 72 | setbits_8(&gpio->par_cs, GPIO_PAR_CS4); |
| 73 | out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); |
| 74 | out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); |
| 75 | out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 76 | #endif |
| 77 | |
| 78 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ |
| 79 | && defined(CONFIG_SYS_CS5_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 80 | setbits_8(&gpio->par_cs, GPIO_PAR_CS5); |
| 81 | out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); |
| 82 | out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); |
| 83 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 84 | #endif |
| 85 | |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 86 | #ifdef CONFIG_SYS_I2C_FSL |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 87 | out_8(&gpio->par_feci2c, |
| 88 | GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 89 | #endif |
| 90 | |
| 91 | icache_enable(); |
| 92 | } |
| 93 | |
| 94 | /* initialize higher level parts of CPU like timers */ |
| 95 | int cpu_init_r(void) |
| 96 | { |
| 97 | #ifdef CONFIG_MCFFEC |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 98 | u32 fec_mii_base0, fec_mii_base1; |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 99 | ccm_t *ccm = (ccm_t *) MMAP_CCM; |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 100 | #endif |
| 101 | #ifdef CONFIG_MCFRTC |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 102 | rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); |
| 103 | rtcex_t *rtcex = (rtcex_t *) &rtc->extended; |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 104 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 105 | out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); |
| 106 | out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 107 | |
| 108 | #endif |
| 109 | #ifdef CONFIG_MCFFEC |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 110 | fec_get_mii_base(0, &fec_mii_base0); |
| 111 | fec_get_mii_base(1, &fec_mii_base1); |
| 112 | |
| 113 | if (fec_mii_base0 != fec_mii_base1) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 114 | setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 115 | else |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 116 | clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 117 | #endif |
| 118 | |
| 119 | return (0); |
| 120 | } |
| 121 | |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 122 | void uart_port_conf(int port) |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 123 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 124 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 125 | |
| 126 | /* Setup Ports: */ |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 127 | switch (port) { |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 128 | case 0: |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 129 | clrbits_8(&gpio->par_uart, |
| 130 | GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); |
| 131 | setbits_8(&gpio->par_uart, |
| 132 | GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 133 | break; |
| 134 | case 1: |
| 135 | #ifdef CONFIG_SYS_UART1_ALT1_GPIO |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 136 | clrbits_8(&gpio->par_simp1h, |
| 137 | GPIO_PAR_SIMP1H_DATA1_UNMASK | |
| 138 | GPIO_PAR_SIMP1H_VEN1_UNMASK); |
| 139 | setbits_8(&gpio->par_simp1h, |
| 140 | GPIO_PAR_SIMP1H_DATA1_U1TXD | |
| 141 | GPIO_PAR_SIMP1H_VEN1_U1RXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 142 | #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 143 | clrbits_8(&gpio->par_ssih, |
| 144 | GPIO_PAR_SSIH_RXD_UNMASK | |
| 145 | GPIO_PAR_SSIH_TXD_UNMASK); |
| 146 | setbits_8(&gpio->par_ssih, |
| 147 | GPIO_PAR_SSIH_RXD_U1RXD | |
| 148 | GPIO_PAR_SSIH_TXD_U1TXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 149 | #endif |
| 150 | break; |
| 151 | case 2: |
| 152 | #ifdef CONFIG_SYS_UART2_PRI_GPIO |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 153 | setbits_8(&gpio->par_uart, |
| 154 | GPIO_PAR_UART_U2TXD | |
| 155 | GPIO_PAR_UART_U2RXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 156 | #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 157 | clrbits_8(&gpio->par_dspih, |
| 158 | GPIO_PAR_DSPIH_SIN_UNMASK | |
| 159 | GPIO_PAR_DSPIH_SOUT_UNMASK); |
| 160 | setbits_8(&gpio->par_dspih, |
| 161 | GPIO_PAR_DSPIH_SIN_U2RXD | |
| 162 | GPIO_PAR_DSPIH_SOUT_U2TXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 163 | #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 164 | clrbits_8(&gpio->par_feci2c, |
| 165 | GPIO_PAR_FECI2C_SDA_UNMASK | |
| 166 | GPIO_PAR_FECI2C_SCL_UNMASK); |
| 167 | setbits_8(&gpio->par_feci2c, |
| 168 | GPIO_PAR_FECI2C_SDA_U2TXD | |
| 169 | GPIO_PAR_FECI2C_SCL_U2RXD); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 170 | #endif |
| 171 | break; |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | #if defined(CONFIG_CMD_NET) |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 176 | int fecpin_setclear(fec_info_t *info, int setclear) |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 177 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 178 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 179 | u32 fec0_base; |
| 180 | |
| 181 | if (fec_get_base_addr(0, &fec0_base)) |
| 182 | return -1; |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 183 | |
| 184 | if (setclear) { |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 185 | if (info->iobase == fec0_base) { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 186 | setbits_8(&gpio->par_fec, |
| 187 | GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); |
| 188 | setbits_8(&gpio->par_feci2c, |
| 189 | GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 190 | } else { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 191 | setbits_8(&gpio->par_fec, |
| 192 | GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); |
| 193 | setbits_8(&gpio->par_feci2c, |
| 194 | GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 195 | } |
| 196 | } else { |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 197 | if (info->iobase == fec0_base) { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 198 | clrbits_8(&gpio->par_fec, |
| 199 | GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); |
| 200 | clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 201 | } else { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 202 | clrbits_8(&gpio->par_fec, |
| 203 | GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); |
| 204 | clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 205 | } |
| 206 | } |
| 207 | return 0; |
| 208 | } |
| 209 | #endif /* CONFIG_CMD_NET */ |
| 210 | #endif /* CONFIG_MCF5301x */ |
| 211 | |
| 212 | #ifdef CONFIG_MCF532x |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 213 | void cpu_init_f(void) |
| 214 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 215 | scm1_t *scm1 = (scm1_t *) MMAP_SCM1; |
| 216 | scm2_t *scm2 = (scm2_t *) MMAP_SCM2; |
| 217 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| 218 | fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; |
Simon Glass | 660031e | 2014-06-07 22:07:58 -0600 | [diff] [blame] | 219 | #ifndef CONFIG_WATCHDOG |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 220 | wdog_t *wdog = (wdog_t *) MMAP_WDOG; |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 221 | |
| 222 | /* watchdog is enabled by default - disable the watchdog */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 223 | out_be16(&wdog->cr, 0); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 224 | #endif |
| 225 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 226 | out_be32(&scm1->mpr0, 0x77777777); |
| 227 | out_be32(&scm2->pacra, 0); |
| 228 | out_be32(&scm2->pacrb, 0); |
| 229 | out_be32(&scm2->pacrc, 0); |
| 230 | out_be32(&scm2->pacrd, 0); |
| 231 | out_be32(&scm2->pacre, 0); |
| 232 | out_be32(&scm2->pacrf, 0); |
| 233 | out_be32(&scm2->pacrg, 0); |
| 234 | out_be32(&scm1->pacrh, 0); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 235 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 236 | /* Port configuration */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 237 | out_8(&gpio->par_cs, 0); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 238 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 239 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ |
| 240 | && defined(CONFIG_SYS_CS0_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 241 | out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); |
| 242 | out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); |
| 243 | out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 244 | #endif |
| 245 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 246 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ |
| 247 | && defined(CONFIG_SYS_CS1_CTRL)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 248 | /* Latch chipselect */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 249 | setbits_8(&gpio->par_cs, GPIO_PAR_CS1); |
| 250 | out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); |
| 251 | out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); |
| 252 | out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 253 | #endif |
| 254 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 255 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ |
| 256 | && defined(CONFIG_SYS_CS2_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 257 | setbits_8(&gpio->par_cs, GPIO_PAR_CS2); |
| 258 | out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); |
| 259 | out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); |
| 260 | out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 261 | #endif |
| 262 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 263 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ |
| 264 | && defined(CONFIG_SYS_CS3_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 265 | setbits_8(&gpio->par_cs, GPIO_PAR_CS3); |
| 266 | out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); |
| 267 | out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); |
| 268 | out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 269 | #endif |
| 270 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 271 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ |
| 272 | && defined(CONFIG_SYS_CS4_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 273 | setbits_8(&gpio->par_cs, GPIO_PAR_CS4); |
| 274 | out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); |
| 275 | out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); |
| 276 | out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 277 | #endif |
| 278 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 279 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ |
| 280 | && defined(CONFIG_SYS_CS5_CTRL)) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 281 | setbits_8(&gpio->par_cs, GPIO_PAR_CS5); |
| 282 | out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); |
| 283 | out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); |
| 284 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 285 | #endif |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 286 | |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 287 | #ifdef CONFIG_SYS_I2C_FSL |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 288 | out_8(&gpio->par_feci2c, |
| 289 | GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); |
TsiChungLiew | 2325c9f | 2007-08-05 05:15:18 -0500 | [diff] [blame] | 290 | #endif |
| 291 | |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 292 | icache_enable(); |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /* |
| 296 | * initialize higher level parts of CPU like timers |
| 297 | */ |
| 298 | int cpu_init_r(void) |
| 299 | { |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 300 | return (0); |
| 301 | } |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 302 | |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 303 | void uart_port_conf(int port) |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 304 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 305 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 306 | |
| 307 | /* Setup Ports: */ |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 308 | switch (port) { |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 309 | case 0: |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 310 | clrbits_be16(&gpio->par_uart, |
| 311 | GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); |
| 312 | setbits_be16(&gpio->par_uart, |
| 313 | GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 314 | break; |
| 315 | case 1: |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 316 | clrbits_be16(&gpio->par_uart, |
| 317 | GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); |
| 318 | setbits_be16(&gpio->par_uart, |
| 319 | GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 320 | break; |
| 321 | case 2: |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 322 | #ifdef CONFIG_SYS_UART2_ALT1_GPIO |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 323 | clrbits_8(&gpio->par_timer, 0xf0); |
| 324 | setbits_8(&gpio->par_timer, |
| 325 | GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 326 | #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 327 | clrbits_8(&gpio->par_feci2c, 0x00ff); |
| 328 | setbits_8(&gpio->par_feci2c, |
| 329 | GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 330 | #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 331 | clrbits_be16(&gpio->par_ssi, 0x0f00); |
| 332 | setbits_be16(&gpio->par_ssi, |
| 333 | GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); |
TsiChung Liew | f9556a7 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 334 | #endif |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 335 | break; |
| 336 | } |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | #if defined(CONFIG_CMD_NET) |
Angelo Durgehello | 8ff47f7 | 2019-11-15 23:54:16 +0100 | [diff] [blame] | 340 | int fecpin_setclear(fec_info_t *info, int setclear) |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 341 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 342 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 343 | |
| 344 | if (setclear) { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 345 | setbits_8(&gpio->par_fec, |
| 346 | GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); |
| 347 | setbits_8(&gpio->par_feci2c, |
| 348 | GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 349 | } else { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 350 | clrbits_8(&gpio->par_fec, |
| 351 | GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); |
| 352 | clrbits_8(&gpio->par_feci2c, |
| 353 | GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 354 | } |
| 355 | return 0; |
TsiChungLiew | 74634c8 | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 356 | } |
TsiChung Liew | 69b1757 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 357 | #endif |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 358 | #endif /* CONFIG_MCF532x */ |