Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014-2016, Freescale Semiconductor, Inc. |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 33d1e70 | 2019-11-14 12:57:32 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 8 | #include <asm/cache.h> |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 9 | #include <asm/io.h> |
| 10 | #include <asm/system.h> |
| 11 | #include <asm/armv8/mmu.h> |
| 12 | #include <asm/io.h> |
| 13 | #include <asm/arch/mc_me_regs.h> |
| 14 | #include "cpu.h" |
| 15 | |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 16 | u32 cpu_mask(void) |
| 17 | { |
| 18 | return readl(MC_ME_CS); |
| 19 | } |
| 20 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 21 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 22 | |
| 23 | #define S32V234_IRAM_BASE 0x3e800000UL |
| 24 | #define S32V234_IRAM_SIZE 0x800000UL |
| 25 | #define S32V234_DRAM_BASE1 0x80000000UL |
| 26 | #define S32V234_DRAM_SIZE1 0x40000000UL |
| 27 | #define S32V234_DRAM_BASE2 0xC0000000UL |
| 28 | #define S32V234_DRAM_SIZE2 0x20000000UL |
| 29 | #define S32V234_PERIPH_BASE 0x40000000UL |
| 30 | #define S32V234_PERIPH_SIZE 0x40000000UL |
| 31 | |
| 32 | static struct mm_region s32v234_mem_map[] = { |
| 33 | { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 34 | .virt = S32V234_IRAM_BASE, |
| 35 | .phys = S32V234_IRAM_BASE, |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 36 | .size = S32V234_IRAM_SIZE, |
| 37 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 38 | PTE_BLOCK_OUTER_SHARE |
| 39 | }, { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 40 | .virt = S32V234_DRAM_BASE1, |
| 41 | .phys = S32V234_DRAM_BASE1, |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 42 | .size = S32V234_DRAM_SIZE1, |
| 43 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 44 | PTE_BLOCK_OUTER_SHARE |
| 45 | }, { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 46 | .virt = S32V234_PERIPH_BASE, |
| 47 | .phys = S32V234_PERIPH_BASE, |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 48 | .size = S32V234_PERIPH_SIZE, |
| 49 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 50 | PTE_BLOCK_NON_SHARE |
| 51 | /* TODO: Do we need these? */ |
| 52 | /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */ |
| 53 | }, { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 54 | .virt = S32V234_DRAM_BASE2, |
| 55 | .phys = S32V234_DRAM_BASE2, |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 56 | .size = S32V234_DRAM_SIZE2, |
| 57 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | |
| 58 | PTE_BLOCK_OUTER_SHARE |
| 59 | }, { |
| 60 | /* List terminator */ |
| 61 | 0, |
| 62 | } |
| 63 | }; |
| 64 | |
| 65 | struct mm_region *mem_map = s32v234_mem_map; |
| 66 | |
| 67 | #endif |
| 68 | |
| 69 | /* |
| 70 | * Return the number of cores on this SOC. |
| 71 | */ |
| 72 | int cpu_numcores(void) |
| 73 | { |
| 74 | int numcores; |
| 75 | u32 mask; |
| 76 | |
| 77 | mask = cpu_mask(); |
| 78 | numcores = hweight32(cpu_mask()); |
| 79 | |
| 80 | /* Verify if M4 is deactivated */ |
| 81 | if (mask & 0x1) |
| 82 | numcores--; |
| 83 | |
| 84 | return numcores; |
| 85 | } |
| 86 | |
| 87 | #if defined(CONFIG_ARCH_EARLY_INIT_R) |
| 88 | int arch_early_init_r(void) |
| 89 | { |
| 90 | int rv; |
| 91 | asm volatile ("dsb sy"); |
| 92 | rv = fsl_s32v234_wake_seconday_cores(); |
| 93 | |
| 94 | if (rv) |
| 95 | printf("Did not wake secondary cores\n"); |
| 96 | |
| 97 | asm volatile ("sev"); |
| 98 | return 0; |
| 99 | } |
| 100 | #endif /* CONFIG_ARCH_EARLY_INIT_R */ |