| Stephen Warren | d010783 | 2016-05-13 15:50:29 -0600 | [diff] [blame] | 1 | menu "Mailbox Controller Support" |
| 2 | |
| 3 | config DM_MAILBOX |
| 4 | bool "Enable mailbox controllers using Driver Model" |
| 5 | depends on DM && OF_CONTROL |
| 6 | help |
| 7 | Enable support for the mailbox driver class. Mailboxes provide the |
| 8 | ability to transfer small messages and/or notifications from one |
| 9 | CPU to another CPU, or sometimes to dedicated HW modules. They form |
| 10 | the basis of a variety of inter-process/inter-CPU communication |
| 11 | protocols. |
| 12 | |
| Mark Kettenis | f3efb3b | 2022-01-22 20:38:12 +0100 | [diff] [blame] | 13 | config APPLE_MBOX |
| 14 | bool "Enable Apple IOP controller support" |
| 15 | depends on DM_MAILBOX && ARCH_APPLE |
| 16 | default y |
| 17 | help |
| 18 | Enable support for the mailboxes that provide a comminucation |
| 19 | channel with Apple IOP controllers integrated on Apple SoCs. |
| 20 | These IOP controllers are used to implement various functions |
| 21 | such as the System Management Controller (SMC) and NVMe and this |
| 22 | driver is required to get that functionality up and running. |
| 23 | |
| Stephen Warren | 62f2c90 | 2016-05-16 17:41:37 -0600 | [diff] [blame] | 24 | config SANDBOX_MBOX |
| 25 | bool "Enable the sandbox mailbox test driver" |
| 26 | depends on DM_MAILBOX && SANDBOX |
| 27 | help |
| 28 | Enable support for a test mailbox implementation, which simply echos |
| 29 | back a modified version of any message that is sent. |
| 30 | |
| Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 31 | config TEGRA_HSP |
| 32 | bool "Enable Tegra HSP controller support" |
| Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 33 | depends on DM_MAILBOX && ARCH_TEGRA |
| Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 34 | help |
| 35 | This enables support for the NVIDIA Tegra HSP Hw module, which |
| 36 | implements doorbells, mailboxes, semaphores, and shared interrupts. |
| 37 | |
| Fabien Dessenne | ac0da89 | 2019-05-14 11:20:34 +0200 | [diff] [blame] | 38 | config STM32_IPCC |
| 39 | bool "Enable STM32 IPCC controller support" |
| 40 | depends on DM_MAILBOX && ARCH_STM32MP |
| 41 | help |
| 42 | This enables support for the STM32MP IPCC Hw module, which |
| 43 | implements doorbells between 2 processors. |
| 44 | |
| Lokesh Vutla | bb6d08d | 2018-08-27 15:57:48 +0530 | [diff] [blame] | 45 | config K3_SEC_PROXY |
| 46 | bool "Texas Instruments K3 Secure Proxy Driver" |
| 47 | depends on DM_MAILBOX && ARCH_K3 |
| 48 | help |
| 49 | An implementation of Secure proxy slave driver for K3 SoCs from |
| 50 | Texas Instruments. Secure proxy is a communication entity mainly |
| 51 | used for communication between multiple processors with the SoC. |
| 52 | Select this driver if your platform has support for this hardware |
| 53 | block. |
| 54 | |
| Ibai Erkiaga | 4b1264d | 2019-09-27 11:36:56 +0100 | [diff] [blame] | 55 | config ZYNQMP_IPI |
| 56 | bool "Xilinx ZynqMP IPI controller support" |
| Ashok Reddy Soma | 0b33d69 | 2022-07-22 02:46:58 -0600 | [diff] [blame] | 57 | depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL) |
| Ibai Erkiaga | 4b1264d | 2019-09-27 11:36:56 +0100 | [diff] [blame] | 58 | help |
| 59 | This enables support for the Xilinx ZynqMP Inter Processor Interrupt |
| 60 | communication controller. |
| Stephen Warren | d010783 | 2016-05-13 15:50:29 -0600 | [diff] [blame] | 61 | endmenu |