Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __CONFIG_H |
| 25 | #define __CONFIG_H |
| 26 | /* |
| 27 | * High Level Configuration Options |
| 28 | * (easy to change) |
| 29 | */ |
| 30 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
| 31 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ |
| 32 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ |
| 33 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ |
| 34 | #define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ |
| 35 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 36 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 37 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 38 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * Command line configuration. |
| 42 | */ |
| 43 | #include <config_cmd_default.h> |
| 44 | |
| 45 | #define CONFIG_CMD_ASKENV |
| 46 | #define CONFIG_CMD_ELF |
| 47 | #define CONFIG_CMD_IMMAP |
| 48 | #define CONFIG_CMD_NET |
| 49 | #define CONFIG_CMD_PING |
| 50 | #define CONFIG_CMD_REGINFO |
| 51 | |
Jean-Christophe PLAGNIOL-VILLARD | 4134872 | 2008-01-25 07:54:47 +0100 | [diff] [blame] | 52 | #if defined(CONFIG_CMD_KGDB) |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 53 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 54 | #endif |
| 55 | |
| 56 | /* |
| 57 | * Serial console configuration |
| 58 | */ |
| 59 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
| 60 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
| 61 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 62 | |
| 63 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
| 64 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 65 | #undef CONFIG_BOOTARGS |
| 66 | |
| 67 | #define CONFIG_PREBOOT "echo;" \ |
| 68 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ |
| 69 | "echo" |
| 70 | |
| 71 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 72 | "netdev=eth0\0" \ |
| 73 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 74 | "nfsroot=$(serverip):$(rootpath)\0" \ |
| 75 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 76 | "addip=setenv bootargs $(bootargs) " \ |
| 77 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ |
| 78 | ":$(hostname):$(netdev):off panic=5\0" \ |
| 79 | "flash_nfs=run nfsargs addip;" \ |
| 80 | "bootm $(kernel_addr)\0" \ |
| 81 | "flash_self=run ramargs addip;" \ |
| 82 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ |
| 83 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ |
| 84 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
| 85 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ |
| 86 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ |
| 87 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ |
| 88 | "" |
| 89 | #define CONFIG_BOOTCOMMAND "run net_nfs" |
| 90 | |
| 91 | /* |
| 92 | * IPB Bus clocking configuration. |
| 93 | */ |
| 94 | #define CFG_IPBSPEED_133 /* define for 133MHz speed */ |
| 95 | #if defined(CFG_IPBSPEED_133) |
| 96 | /* |
| 97 | * PCI Bus clocking configuration |
| 98 | * |
| 99 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if |
| 100 | * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
| 101 | * been tested with a IPB Bus Clock of 66 MHz. |
| 102 | */ |
| 103 | #define CFG_PCISPEED_66 /* define for 66MHz speed */ |
| 104 | #else |
| 105 | #undef CFG_PCISPEED_66 /* for 33MHz speed */ |
| 106 | #endif |
| 107 | |
| 108 | /* |
| 109 | * Memory map |
| 110 | */ |
| 111 | #define CFG_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ |
Heiko Schocher | 9a8118b | 2008-01-11 15:15:16 +0100 | [diff] [blame] | 112 | |
| 113 | #define CFG_DEFAULT_MBAR 0x80000000 |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 114 | #define CFG_SDRAM_BASE 0x00000000 |
| 115 | /* Use SRAM until RAM will be available */ |
| 116 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
| 117 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ |
| 118 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 119 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 120 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 121 | |
| 122 | #define CFG_MONITOR_BASE TEXT_BASE |
| 123 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 124 | # define CFG_RAMBOOT 1 |
| 125 | #endif |
| 126 | |
| 127 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 128 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 129 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 130 | |
| 131 | /* |
| 132 | * Flash configuration |
| 133 | */ |
| 134 | #define CFG_FLASH_BASE 0xFF000000 |
| 135 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 136 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 137 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
| 138 | #define CFG_FLASH_EMPTY_INFO |
| 139 | #define CFG_FLASH_SIZE 0x01000000 /* 16 MByte */ |
| 140 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
| 141 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ |
| 142 | #define CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ |
| 143 | |
| 144 | /* |
| 145 | * Chip selects configuration |
| 146 | */ |
| 147 | /* Boot Chipselect */ |
| 148 | #define CFG_BOOTCS_START CFG_FLASH_BASE |
| 149 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
| 150 | #define CFG_BOOTCS_CFG 0x00047800 |
| 151 | |
| 152 | /* |
| 153 | * Environment settings |
| 154 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 155 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 156 | #define CONFIG_ENV_OFFSET 0x40000 |
| 157 | #define CONFIG_ENV_ADDR (TEXT_BASE + CONFIG_ENV_OFFSET) |
| 158 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 159 | #define CONFIG_ENV_SIZE 0x4000 |
| 160 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
| 161 | #define CONFIG_ENV_ADDR_REDUND (TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) |
| 162 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Heiko Schocher | a1d7c2d | 2008-01-11 15:15:15 +0100 | [diff] [blame] | 163 | #define CONFIG_ENV_OVERWRITE 1 |
| 164 | |
| 165 | /* |
| 166 | * Ethernet configuration |
| 167 | */ |
| 168 | #define CONFIG_MPC5xxx_FEC 1 |
| 169 | #define CONFIG_PHY_ADDR 0x01 |
| 170 | #define CONFIG_MII 1 |
| 171 | |
| 172 | /* |
| 173 | * GPIO configuration |
| 174 | */ |
| 175 | #define CFG_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD |
| 176 | no PCI */ |
| 177 | |
| 178 | /* |
| 179 | * Miscellaneous configurable options |
| 180 | */ |
| 181 | #define CFG_LONGHELP /* undef to save memory */ |
| 182 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 183 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 184 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 185 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 186 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 187 | |
| 188 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
| 189 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
| 190 | |
| 191 | #define CFG_LOAD_ADDR 0x200000 /* default load address */ |
| 192 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 193 | |
| 194 | #define CONFIG_DISPLAY_BOARDINFO 1 |
| 195 | #define CONFIG_CMDLINE_EDITING 1 |
| 196 | |
| 197 | /* |
| 198 | * Various low-level settings |
| 199 | */ |
| 200 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
| 201 | #define CFG_HID0_FINAL HID0_ICE |
| 202 | |
| 203 | #define CFG_CS_BURST 0x00000000 |
| 204 | #define CFG_CS_DEADCYCLE 0x33333333 |
| 205 | #define CFG_RESET_ADDRESS 0xff000000 |
| 206 | |
| 207 | /* pass open firmware flat tree */ |
| 208 | #define CONFIG_OF_LIBFDT 1 |
| 209 | #define CONFIG_OF_BOARD_SETUP 1 |
| 210 | |
| 211 | #define OF_CPU "PowerPC,5200@0" |
| 212 | #define OF_TBCLK (bd->bi_busfreq / 4) |
| 213 | #define OF_SOC "soc5200@f0000000" |
| 214 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
| 215 | |
| 216 | #endif /* __CONFIG_H */ |