blob: 5bf5d8b0e24abb4c4094828155f8b5543f8c1bc5 [file] [log] [blame]
Simon Glass837a66a2019-12-06 21:42:53 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017 Intel Corp.
4 * Copyright 2019 Google LLC
5 *
6 * Taken partly from coreboot gpio.c
7 *
8 * Pinctrl is modelled as a separate device-tree node and device for each
9 * 'community' (basically a set of GPIOs). The separate devices work together
10 * and many functions permit any PINCTRL device to be provided as a parameter,
11 * since the pad numbering is unique across all devices.
12 *
13 * Each pinctrl has a single child GPIO device to handle GPIO access and
14 * therefore there is a simple GPIO driver included in this file.
15 */
16
17#define LOG_CATEGORY UCLASS_GPIO
18
19#include <common.h>
20#include <dm.h>
21#include <irq.h>
22#include <p2sb.h>
23#include <spl.h>
24#include <asm-generic/gpio.h>
25#include <asm/intel_pinctrl.h>
26#include <asm/intel_pinctrl_defs.h>
27#include <asm/arch/gpio.h>
Wolfgang Wallner97132162020-01-22 16:01:45 +010028#include <asm/itss.h>
Simon Glass837a66a2019-12-06 21:42:53 -070029#include <dm/device-internal.h>
30#include <dt-bindings/gpio/gpio.h>
31
32#define GPIO_DW_SIZE(x) (sizeof(u32) * (x))
33#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num))
34#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0)
35#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1)
36
37#define MISCCFG_GPE0_DW0_SHIFT 8
38#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
39#define MISCCFG_GPE0_DW1_SHIFT 12
40#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
41#define MISCCFG_GPE0_DW2_SHIFT 16
42#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
43
44#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \
45 ((group) * sizeof(u32)))
46#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
47 ((group) * sizeof(u32)))
48#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
49 ((group) * sizeof(uint32_t)))
50#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
51 ((group) * sizeof(uint32_t)))
52
53/**
54 * relative_pad_in_comm() - Get the relative position of a GPIO
55 *
56 * This finds the position of a GPIO within a community
57 *
58 * @comm: Community to search
59 * @gpio: Pad number to look up (assumed to be valid)
60 * @return offset, 0 for first GPIO in community
61 */
62static size_t relative_pad_in_comm(const struct pad_community *comm,
63 uint gpio)
64{
65 return gpio - comm->first_pad;
66}
67
68/**
69 * pinctrl_group_index() - Find group for a a pad
70 *
71 * Find the group within the community that the pad is a part of
72 *
73 * @comm: Community to search
74 * @relative_pad: Pad to look up
75 * @return group number if found (see community_n_groups, etc.), or
76 * -ESPIPE if no groups, or -ENOENT if not found
77 */
78static int pinctrl_group_index(const struct pad_community *comm,
79 uint relative_pad)
80{
81 int i;
82
83 if (!comm->groups)
84 return -ESPIPE;
85
86 /* find the base pad number for this pad's group */
87 for (i = 0; i < comm->num_groups; i++) {
88 if (relative_pad >= comm->groups[i].first_pad &&
89 relative_pad < comm->groups[i].first_pad +
90 comm->groups[i].size)
91 return i;
92 }
93
94 return -ENOENT;
95}
96
97static int pinctrl_group_index_scaled(const struct pad_community *comm,
98 uint relative_pad, size_t scale)
99{
100 int ret;
101
102 ret = pinctrl_group_index(comm, relative_pad);
103 if (ret < 0)
104 return ret;
105
106 return ret * scale;
107}
108
109static int pinctrl_within_group(const struct pad_community *comm,
110 uint relative_pad)
111{
112 int ret;
113
114 ret = pinctrl_group_index(comm, relative_pad);
115 if (ret < 0)
116 return ret;
117
118 return relative_pad - comm->groups[ret].first_pad;
119}
120
121static u32 pinctrl_bitmask_within_group(const struct pad_community *comm,
122 uint relative_pad)
123{
124 return 1U << pinctrl_within_group(comm, relative_pad);
125}
126
127/**
128 * pinctrl_get_device() - Find the device for a particular pad
129 *
130 * Each pinctr, device is attached to one community and this supports a number
131 * of pads. This function finds the device which controls a particular pad.
132 *
133 * @pad: Pad to check
134 * @devp: Returns the device for that pad
135 * @return 0 if OK, -ENOTBLK if no device was found for the given pin
136 */
137static int pinctrl_get_device(uint pad, struct udevice **devp)
138{
139 struct udevice *dev;
140
141 /*
142 * We have to probe each one of these since the community link is only
143 * attached in intel_pinctrl_ofdata_to_platdata().
144 */
145 uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
146 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
147 const struct pad_community *comm = priv->comm;
148
149 if (pad >= comm->first_pad && pad <= comm->last_pad) {
150 *devp = dev;
151 return 0;
152 }
153 }
154 printf("pad %d not found\n", pad);
155
156 return -ENOTBLK;
157}
158
159int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp)
160{
161 const struct pad_community *comm;
162 struct intel_pinctrl_priv *priv;
163 struct udevice *dev;
164 int ret;
165
166 ret = pinctrl_get_device(pad, &dev);
167 if (ret)
168 return log_msg_ret("pad", ret);
169 priv = dev_get_priv(dev);
170 comm = priv->comm;
171 *devp = dev;
172 *offsetp = relative_pad_in_comm(comm, pad);
173
174 return 0;
175}
176
177static int pinctrl_configure_owner(struct udevice *dev,
178 const struct pad_config *cfg,
179 const struct pad_community *comm)
180{
181 u32 hostsw_own;
182 u16 hostsw_own_offset;
183 int pin;
184 int ret;
185
186 pin = relative_pad_in_comm(comm, cfg->pad);
187
188 /*
189 * Based on the gpio pin number configure the corresponding bit in
190 * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
191 */
192 hostsw_own_offset = comm->host_own_reg_0;
193 ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32));
194 if (ret < 0)
195 return ret;
196 hostsw_own_offset += ret;
197
198 hostsw_own = pcr_read32(dev, hostsw_own_offset);
199
200 /*
201 *The 4th bit in pad_config 1 (RO) is used to indicate if the pad
202 * needs GPIO driver ownership. Set the bit if GPIO driver ownership
203 * requested, otherwise clear the bit.
204 */
205 if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
206 hostsw_own |= pinctrl_bitmask_within_group(comm, pin);
207 else
208 hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin);
209
210 pcr_write32(dev, hostsw_own_offset, hostsw_own);
211
212 return 0;
213}
214
215static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg,
216 const struct pad_community *comm)
217{
218 u32 value;
219 u16 sts_reg;
220 u16 en_reg;
221 int group;
222 int pin;
223 int ret;
224
225 if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
226 return 0;
227
228 pin = relative_pad_in_comm(comm, cfg->pad);
229 ret = pinctrl_group_index(comm, pin);
230 if (ret < 0)
231 return ret;
232 group = ret;
233
234 sts_reg = GPI_SMI_STS_OFFSET(comm, group);
235 value = pcr_read32(dev, sts_reg);
236 /* Write back 1 to reset the sts bits */
237 pcr_write32(dev, sts_reg, value);
238
239 /* Set enable bits */
240 en_reg = GPI_SMI_EN_OFFSET(comm, group);
241 pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin));
242
243 return 0;
244}
245
246static int pinctrl_configure_itss(struct udevice *dev,
247 const struct pad_config *cfg,
248 uint pad_cfg_offset)
249{
250 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
251
252 if (!priv->itss_pol_cfg)
253 return -ENOSYS;
254
255 int irq;
256
257 /*
258 * Set up ITSS polarity if pad is routed to APIC.
259 *
260 * The ITSS takes only active high interrupt signals. Therefore,
261 * if the pad configuration indicates an inversion assume the
262 * intent is for the ITSS polarity. Before forwarding on the
263 * request to the APIC there's an inversion setting for how the
264 * signal is forwarded to the APIC. Honor the inversion setting
265 * in the GPIO pad configuration so that a hardware active low
266 * signal looks that way to the APIC (double inversion).
267 */
268 if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
269 return 0;
270
271 irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
272 irq &= PAD_CFG1_IRQ_MASK;
273 if (!irq) {
274 log_err("GPIO %u doesn't support APIC routing\n", cfg->pad);
275
276 return -EPROTONOSUPPORT;
277 }
278 irq_set_polarity(priv->itss, irq,
279 cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT);
280
281 return 0;
282}
283
284/* Number of DWx config registers can be different for different SOCs */
285static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad)
286{
287 const struct pad_community *comm = priv->comm;
288 size_t offset;
289
290 offset = relative_pad_in_comm(comm, pad);
291 offset *= GPIO_DW_SIZE(priv->num_cfgs);
292
293 return offset + comm->pad_cfg_base;
294}
295
296static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
297 u32 config_value)
298{
299 const struct reset_mapping *rst_map = comm->reset_map;
300 int i;
301
302 /* Logical reset values equal chipset values */
303 if (!rst_map || !comm->num_reset_vals)
304 return config_value;
305
306 for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
307 if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
308 config_value &= ~PAD_CFG0_RESET_MASK;
309 config_value |= rst_map->chipset;
310
311 return config_value;
312 }
313 }
314 log_err("Logical-to-Chipset mapping not found\n");
315
316 return -ENOENT;
317}
318
319static const int mask[4] = {
320 PAD_CFG0_TX_STATE |
321 PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |
322 PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK |
323 PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL |
324 PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK |
325 PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK,
326
327#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY
328 PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK,
329#else
330 PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK,
331#endif
332
333 PAD_CFG2_DEBOUNCE_MASK,
334
335 0,
336};
337
338/**
339 * pinctrl_configure_pad() - Configure a pad
340 *
341 * @dev: Pinctrl device containing the pad (see pinctrl_get_device())
342 * @cfg: Configuration to apply
343 * @return 0 if OK, -ve on error
344 */
345static int pinctrl_configure_pad(struct udevice *dev,
346 const struct pad_config *cfg)
347{
348 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
349 const struct pad_community *comm = priv->comm;
350 uint config_offset;
351 u32 pad_conf, soc_pad_conf;
352 int ret;
353 int i;
354
355 if (IS_ERR(comm))
356 return PTR_ERR(comm);
357 config_offset = pad_config_offset(priv, cfg->pad);
358 for (i = 0; i < priv->num_cfgs; i++) {
359 pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i));
360
361 soc_pad_conf = cfg->pad_config[i];
362 if (i == 0) {
363 ret = pinctrl_pad_reset_config_override(comm,
364 soc_pad_conf);
365 if (ret < 0)
366 return ret;
367 soc_pad_conf = ret;
368 }
369 soc_pad_conf &= mask[i];
370 soc_pad_conf |= pad_conf & ~mask[i];
371
372 log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n",
373 comm->port, relative_pad_in_comm(comm, cfg->pad), i,
374 pad_conf,/* old value */
375 /* value passed from pinctrl table */
376 cfg->pad_config[i],
377 soc_pad_conf); /*new value*/
378 pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i),
379 soc_pad_conf);
380 }
381 ret = pinctrl_configure_itss(dev, cfg, config_offset);
382 if (ret && ret != -ENOSYS)
383 return log_msg_ret("itss config failed", ret);
384 ret = pinctrl_configure_owner(dev, cfg, comm);
385 if (ret)
386 return ret;
387 ret = gpi_enable_smi(dev, cfg, comm);
388 if (ret)
389 return ret;
390
391 return 0;
392}
393
394u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
395{
396 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
397 const struct pad_community *comm = priv->comm;
398 uint config_offset;
399
400 assert(device_get_uclass_id(dev) == UCLASS_PINCTRL);
401 config_offset = comm->pad_cfg_base + offset *
402 GPIO_DW_SIZE(priv->num_cfgs);
403
404 return config_offset;
405}
406
407u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
408{
409 uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset);
410
411 return pcr_read32(dev, config_offset);
412}
413
414int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
415{
416 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
417 const struct pad_community *comm = priv->comm;
418 int group;
419
420 group = pinctrl_group_index(comm, offset);
421
422 /* If pad base is not set then use GPIO number as ACPI pin number */
423 if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE)
424 return comm->first_pad + offset;
425
426 /*
427 * If this group has a non-zero pad base then compute the ACPI pin
428 * number from the pad base and the relative pad in the group.
429 */
430 return comm->groups[group].acpi_pad_base +
431 pinctrl_within_group(comm, offset);
432}
433
434int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d)
435{
436 struct udevice *pinctrl_dev;
437 u32 misccfg_value;
438 u32 misccfg_clr;
439 int ret;
440
441 /*
442 * Get the group here for community specific MISCCFG register.
443 * If any of these returns -1 then there is some error in devicetree
444 * where the group is probably hardcoded and does not comply with the
445 * PMC group defines. So we return from here and MISCFG is set to
446 * default.
447 */
448 ret = irq_route_pmc_gpio_gpe(itss, gpe0b);
449 if (ret)
450 return ret;
451 gpe0b = ret;
452
453 ret = irq_route_pmc_gpio_gpe(itss, gpe0c);
454 if (ret)
455 return ret;
456 gpe0c = ret;
457
458 ret = irq_route_pmc_gpio_gpe(itss, gpe0d);
459 if (ret)
460 return ret;
461 gpe0d = ret;
462
463 misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
464 misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
465 misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT;
466
467 /* Program GPIO_MISCCFG */
468 misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK |
469 MISCCFG_GPE0_DW0_MASK;
470
471 log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr,
472 misccfg_value);
473 uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) {
474 pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr,
475 misccfg_value);
476 }
477
478 return 0;
479}
480
481int pinctrl_gpi_clear_int_cfg(void)
482{
483 struct udevice *dev;
484 struct uclass *uc;
485 int ret;
486
487 ret = uclass_get(UCLASS_PINCTRL, &uc);
488 if (ret)
489 return log_msg_ret("pinctrl uc", ret);
490 uclass_foreach_dev(dev, uc) {
491 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
492 const struct pad_community *comm = priv->comm;
493 uint sts_value;
494 int group;
495
496 for (group = 0; group < comm->num_gpi_regs; group++) {
497 /* Clear the enable register */
498 pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0);
499
500 /* Read and clear the set status register bits*/
501 sts_value = pcr_read32(dev,
502 GPI_IS_OFFSET(comm, group));
503 pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value);
504 }
505 }
506
507 return 0;
508}
509
510int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count)
511{
512 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
513 const u32 *ptr;
514 int i;
515
516 log_debug("%s: pads_count=%d\n", __func__, pads_count);
517 for (ptr = pads, i = 0; i < pads_count;
518 ptr += 1 + priv->num_cfgs, i++) {
519 struct udevice *pad_dev = NULL;
520 struct pad_config *cfg;
521 int ret;
522
523 cfg = (struct pad_config *)ptr;
524 ret = pinctrl_get_device(cfg->pad, &pad_dev);
525 if (ret)
526 return ret;
527 ret = pinctrl_configure_pad(pad_dev, cfg);
528 if (ret)
529 return ret;
530 }
531
532 return 0;
533}
534
535int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
536 u32 **padsp, int *pad_countp)
537{
538 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
539 u32 *pads;
540 int size;
541 int ret;
542
543 *padsp = NULL;
544 *pad_countp = 0;
545 size = ofnode_read_size(node, prop);
546 if (size < 0)
547 return 0;
548
549 pads = malloc(size);
550 if (!pads)
551 return -ENOMEM;
552 size /= sizeof(fdt32_t);
553 ret = ofnode_read_u32_array(node, prop, pads, size);
554 if (ret) {
555 free(pads);
556 return ret;
557 }
558 *pad_countp = size / (1 + priv->num_cfgs);
559 *padsp = pads;
560
561 return 0;
562}
563
564int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size)
565{
566 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
567 int count = 0;
568 int i;
569
570 for (i = 0; i < size;) {
571 u32 val;
572 int j;
573
574 for (val = j = 0; j < priv->num_cfgs + 1; j++)
575 val |= pads[i + j];
576 if (!val)
577 break;
578 count++;
579 i += priv->num_cfgs + 1;
580 }
581
582 return count;
583}
584
585int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node)
586{
587 int pads_count;
588 u32 *pads;
589 int ret;
590
591 if (device_get_uclass_id(dev) != UCLASS_PINCTRL)
592 return log_msg_ret("uclass", -EPROTONOSUPPORT);
593 ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count);
594 if (ret)
595 return log_msg_ret("no pads", ret);
596 ret = pinctrl_config_pads(dev, pads, pads_count);
597 free(pads);
598 if (ret)
599 return log_msg_ret("pad config", ret);
600
601 return 0;
602}
603
604int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
605 const struct pad_community *comm,
606 int num_cfgs)
607{
608 struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
609 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
610 int ret;
611
612 if (!comm) {
613 log_err("Cannot find community for pid %d\n", pplat->pid);
614 return -EDOM;
615 }
616 ret = uclass_first_device_err(UCLASS_IRQ, &priv->itss);
617 if (ret)
618 return log_msg_ret("Cannot find ITSS", ret);
619 priv->comm = comm;
620 priv->num_cfgs = num_cfgs;
621
622 return 0;
623}
624
625int intel_pinctrl_probe(struct udevice *dev)
626{
627 struct intel_pinctrl_priv *priv = dev_get_priv(dev);
628
629 priv->itss_pol_cfg = true;
630
631 return 0;
632}
633
634const struct pinctrl_ops intel_pinctrl_ops = {
635 /* No operations are supported, but DM expects this to be present */
636};