wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 3 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 4 | * |
| 5 | * (C) Copyright 2000 |
| 6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <common.h> |
| 28 | #include <watchdog.h> |
| 29 | #include <command.h> |
| 30 | #include <asm/cache.h> |
| 31 | |
| 32 | /* ------------------------------------------------------------------------- */ |
| 33 | |
| 34 | int checkcpu (void) |
| 35 | { |
| 36 | uint pir = get_pir(); |
| 37 | uint pvr = get_pvr(); |
| 38 | |
| 39 | printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir); |
| 40 | switch(pvr) { |
| 41 | default: |
| 42 | printf("PVR=%08x", pvr); |
| 43 | break; |
| 44 | } |
| 45 | |
| 46 | printf("\n"); |
| 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | |
| 52 | /* ------------------------------------------------------------------------- */ |
| 53 | |
| 54 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
| 55 | { |
| 56 | /* |
| 57 | * Initiate hard reset in debug control register DBCR0 |
| 58 | * Make sure MSR[DE] = 1 |
| 59 | */ |
| 60 | __asm__ __volatile__("lis 3, 0x7000" ::: "r3"); |
| 61 | mtspr(DBCR0,3); |
| 62 | return 1; |
| 63 | } |
| 64 | |
| 65 | |
| 66 | /* |
| 67 | * Get timebase clock frequency |
| 68 | */ |
| 69 | unsigned long get_tbclk (void) |
| 70 | { |
| 71 | |
| 72 | sys_info_t sys_info; |
| 73 | |
| 74 | get_sys_info(&sys_info); |
| 75 | return ((sys_info.freqSystemBus + 3L) / 4L); |
| 76 | } |
| 77 | |
| 78 | |
| 79 | #if defined(CONFIG_WATCHDOG) |
| 80 | void |
| 81 | watchdog_reset(void) |
| 82 | { |
| 83 | int re_enable = disable_interrupts(); |
| 84 | reset_85xx_watchdog(); |
| 85 | if (re_enable) enable_interrupts(); |
| 86 | } |
| 87 | |
| 88 | void |
| 89 | reset_85xx_watchdog(void) |
| 90 | { |
| 91 | /* |
| 92 | * Clear TSR(WIS) bit by writing 1 |
| 93 | */ |
| 94 | unsigned long val; |
| 95 | val = mfspr(tsr); |
| 96 | val |= 0x40000000; |
| 97 | mtspr(tsr, val); |
| 98 | } |
| 99 | #endif /* CONFIG_WATCHDOG */ |
| 100 | |
| 101 | #if defined(CONFIG_DDR_ECC) |
| 102 | __inline__ void dcbz(const void* addr) |
| 103 | { |
| 104 | __asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr)); |
| 105 | } |
| 106 | |
| 107 | __inline__ void dcbf(const void* addr) |
| 108 | { |
| 109 | __asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr)); |
| 110 | } |
| 111 | |
| 112 | void dma_init(void) { |
| 113 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 114 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 115 | |
| 116 | dma->satr0 = 0x02c40000; |
| 117 | dma->datr0 = 0x02c40000; |
| 118 | asm("sync; isync; msync"); |
| 119 | return; |
| 120 | } |
| 121 | |
| 122 | uint dma_check(void) { |
| 123 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 124 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 125 | volatile uint status = dma->sr0; |
| 126 | |
| 127 | /* While the channel is busy, spin */ |
| 128 | while((status & 4) == 4) { |
| 129 | status = dma->sr0; |
| 130 | } |
| 131 | |
| 132 | if (status != 0) { |
| 133 | printf ("DMA Error: status = %x\n", status); |
| 134 | } |
| 135 | return status; |
| 136 | } |
| 137 | |
| 138 | int dma_xfer(void *dest, uint count, void *src) { |
| 139 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 140 | volatile ccsr_dma_t *dma = &immap->im_dma; |
| 141 | |
| 142 | dma->dar0 = (uint) dest; |
| 143 | dma->sar0 = (uint) src; |
| 144 | dma->bcr0 = count; |
| 145 | dma->mr0 = 0xf000004; |
| 146 | asm("sync;isync;msync"); |
| 147 | dma->mr0 = 0xf000005; |
| 148 | asm("sync;isync;msync"); |
| 149 | return dma_check(); |
| 150 | } |
| 151 | #endif |