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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +00002/*
3 * Freescale i.MX28 timer driver
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 *
8 * Based on code from LTIB:
9 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
Marek Vasutc140e982011-11-08 23:18:08 +000010 */
11
12#include <common.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070013#include <time.h>
Marek Vasutc140e982011-11-08 23:18:08 +000014#include <asm/io.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/sys_proto.h>
17
18/* Maximum fixed count */
Fadil Berishad608f6e2013-02-27 17:00:07 +000019#if defined(CONFIG_MX23)
20#define TIMER_LOAD_VAL 0xffff
21#elif defined(CONFIG_MX28)
22#define TIMER_LOAD_VAL 0xffffffff
23#endif
Marek Vasutc140e982011-11-08 23:18:08 +000024
25DECLARE_GLOBAL_DATA_PTR;
26
Simon Glass2655ee12012-12-13 20:48:34 +000027#define timestamp (gd->arch.tbl)
Simon Glassa848da52012-12-13 20:48:35 +000028#define lastdec (gd->arch.lastinc)
Marek Vasutc140e982011-11-08 23:18:08 +000029
30/*
31 * This driver uses 1kHz clock source.
32 */
Fadil Berisha69d8ce02013-02-28 10:03:26 -050033#define MXS_INCREMENTER_HZ 1000
Marek Vasutc140e982011-11-08 23:18:08 +000034
35static inline unsigned long tick_to_time(unsigned long tick)
36{
Fadil Berisha69d8ce02013-02-28 10:03:26 -050037 return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
Marek Vasutc140e982011-11-08 23:18:08 +000038}
39
40static inline unsigned long time_to_tick(unsigned long time)
41{
Fadil Berisha69d8ce02013-02-28 10:03:26 -050042 return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
Marek Vasutc140e982011-11-08 23:18:08 +000043}
44
45/* Calculate how many ticks happen in "us" microseconds */
46static inline unsigned long us_to_tick(unsigned long us)
47{
Fadil Berisha69d8ce02013-02-28 10:03:26 -050048 return (us * MXS_INCREMENTER_HZ) / 1000000;
Marek Vasutc140e982011-11-08 23:18:08 +000049}
50
51int timer_init(void)
52{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000053 struct mxs_timrot_regs *timrot_regs =
54 (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +000055
56 /* Reset Timers and Rotary Encoder module */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +000057 mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
Marek Vasutc140e982011-11-08 23:18:08 +000058
59 /* Set fixed_count to 0 */
Fadil Berishad608f6e2013-02-27 17:00:07 +000060#if defined(CONFIG_MX23)
61 writel(0, &timrot_regs->hw_timrot_timcount0);
62#elif defined(CONFIG_MX28)
Marek Vasutc140e982011-11-08 23:18:08 +000063 writel(0, &timrot_regs->hw_timrot_fixed_count0);
Fadil Berishad608f6e2013-02-27 17:00:07 +000064#endif
Marek Vasutc140e982011-11-08 23:18:08 +000065
66 /* Set UPDATE bit and 1Khz frequency */
67 writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
68 TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
69 &timrot_regs->hw_timrot_timctrl0);
70
71 /* Set fixed_count to maximal value */
Fadil Berishad608f6e2013-02-27 17:00:07 +000072#if defined(CONFIG_MX23)
73 writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
74#elif defined(CONFIG_MX28)
Marek Vasutc140e982011-11-08 23:18:08 +000075 writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
Fadil Berishad608f6e2013-02-27 17:00:07 +000076#endif
Marek Vasutc140e982011-11-08 23:18:08 +000077
78 return 0;
79}
80
Marek Vasutc142b672012-02-07 06:47:31 +000081unsigned long long get_ticks(void)
Marek Vasutc140e982011-11-08 23:18:08 +000082{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000083 struct mxs_timrot_regs *timrot_regs =
84 (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
Fadil Berishad608f6e2013-02-27 17:00:07 +000085 uint32_t now;
Marek Vasutc140e982011-11-08 23:18:08 +000086
87 /* Current tick value */
Fadil Berishad608f6e2013-02-27 17:00:07 +000088#if defined(CONFIG_MX23)
89 /* Upper bits are the valid ones. */
90 now = readl(&timrot_regs->hw_timrot_timcount0) >>
91 TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
92#elif defined(CONFIG_MX28)
93 now = readl(&timrot_regs->hw_timrot_running_count0);
Wolfgang Denk1fc42342014-11-06 14:03:04 +010094#else
95#error "Don't know how to read timrot_regs"
Fadil Berishad608f6e2013-02-27 17:00:07 +000096#endif
Marek Vasutc140e982011-11-08 23:18:08 +000097
98 if (lastdec >= now) {
99 /*
100 * normal mode (non roll)
101 * move stamp forward with absolut diff ticks
102 */
103 timestamp += (lastdec - now);
104 } else {
105 /* we have rollover of decrementer */
106 timestamp += (TIMER_LOAD_VAL - now) + lastdec;
107
108 }
109 lastdec = now;
110
Marek Vasutc142b672012-02-07 06:47:31 +0000111 return timestamp;
112}
113
Marek Vasutc142b672012-02-07 06:47:31 +0000114ulong get_timer(ulong base)
115{
Patrick Delaunay9858a602018-10-05 11:33:52 +0200116 return tick_to_time(get_ticks()) - base;
Marek Vasutc142b672012-02-07 06:47:31 +0000117}
118
Marek Vasutc140e982011-11-08 23:18:08 +0000119/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
Fadil Berisha69d8ce02013-02-28 10:03:26 -0500120#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
Marek Vasutc140e982011-11-08 23:18:08 +0000121
122void __udelay(unsigned long usec)
123{
124 uint32_t old, new, incr;
125 uint32_t counter = 0;
126
Fadil Berisha69d8ce02013-02-28 10:03:26 -0500127 old = readl(MXS_HW_DIGCTL_MICROSECONDS);
Marek Vasutc140e982011-11-08 23:18:08 +0000128
129 while (counter < usec) {
Fadil Berisha69d8ce02013-02-28 10:03:26 -0500130 new = readl(MXS_HW_DIGCTL_MICROSECONDS);
Marek Vasutc140e982011-11-08 23:18:08 +0000131
132 /* Check if the timer wrapped. */
133 if (new < old) {
134 incr = 0xffffffff - old;
135 incr += new;
136 } else {
137 incr = new - old;
138 }
139
140 /*
141 * Check if we are close to the maximum time and the counter
142 * would wrap if incremented. If that's the case, break out
143 * from the loop as the requested delay time passed.
144 */
145 if (counter + incr < counter)
146 break;
147
148 counter += incr;
149 old = new;
150 }
151}
Marek Vasutc142b672012-02-07 06:47:31 +0000152
153ulong get_tbclk(void)
154{
Fadil Berisha69d8ce02013-02-28 10:03:26 -0500155 return MXS_INCREMENTER_HZ;
Marek Vasutc142b672012-02-07 06:47:31 +0000156}