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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kever Yang5db9e672017-06-23 16:11:05 +08002/*
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
Kever Yang5db9e672017-06-23 16:11:05 +08004 */
5
6#ifndef _ASM_ARCH_SDRAM_COMMON_H
7#define _ASM_ARCH_SDRAM_COMMON_H
8/*
9 * sys_reg bitfield struct
10 * [31] row_3_4_ch1
11 * [30] row_3_4_ch0
12 * [29:28] chinfo
13 * [27] rank_ch1
14 * [26:25] col_ch1
15 * [24] bk_ch1
16 * [23:22] cs0_row_ch1
17 * [21:20] cs1_row_ch1
18 * [19:18] bw_ch1
19 * [17:16] dbw_ch1;
20 * [15:13] ddrtype
21 * [12] channelnum
22 * [11] rank_ch0
23 * [10:9] col_ch0
24 * [8] bk_ch0
25 * [7:6] cs0_row_ch0
26 * [5:4] cs1_row_ch0
27 * [3:2] bw_ch0
28 * [1:0] dbw_ch0
29*/
30#define SYS_REG_DDRTYPE_SHIFT 13
31#define SYS_REG_DDRTYPE_MASK 7
32#define SYS_REG_NUM_CH_SHIFT 12
33#define SYS_REG_NUM_CH_MASK 1
34#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
35#define SYS_REG_ROW_3_4_MASK 1
36#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
37#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
38#define SYS_REG_RANK_MASK 1
39#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
40#define SYS_REG_COL_MASK 3
41#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
42#define SYS_REG_BK_MASK 1
43#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
44#define SYS_REG_CS0_ROW_MASK 3
45#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
46#define SYS_REG_CS1_ROW_MASK 3
47#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
48#define SYS_REG_BW_MASK 3
49#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
50#define SYS_REG_DBW_MASK 3
51
52/* Get sdram size decode from reg */
53size_t rockchip_sdram_size(phys_addr_t reg);
54
55/* Called by U-Boot board_init_r for Rockchip SoCs */
56int dram_init(void);
57#endif