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git01.mediatek.com / filogic / uboot / 9672848fdb0dcd9fcde54853efa4ffb8582e4494 / . / arch / riscv / dts / microchip-mpfs.dtsi
blob: 4f449a3a9348c40d2c02235bc54b6aa924c78cea [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4#include "dt-bindings/clock/microchip-mpfs-clock.h"
5#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
6#include "dt-bindings/interrupt-controller/riscv-hart.h"
7
8/ {
9 #address-cells = <2>;
10 #size-cells = <2>;
11 model = "Microchip PolarFire SoC";
12 compatible = "microchip,mpfs";
13
14 chosen {
15 };
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 compatible = "sifive,e51", "sifive,rocket0", "riscv";
23 device_type = "cpu";
24 i-cache-block-size = <64>;
25 i-cache-sets = <128>;
26 i-cache-size = <16384>;
27 reg = <0>;
28 riscv,isa = "rv64imac";
29 clocks = <&clkcfg CLK_CPU>;
30 status = "disabled";
31 operating-points = <
32 /* kHz uV */
33 600000 1100000
34 300000 950000
35 150000 750000
36 >;
37 cpu0_intc: interrupt-controller {
38 #interrupt-cells = <1>;
39 compatible = "riscv,cpu-intc";
40 interrupt-controller;
41 };
42 };
43
44 cpu1: cpu@1 {
45 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <32>;
51 device_type = "cpu";
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <32>;
57 mmu-type = "riscv,sv39";
58 reg = <1>;
59 riscv,isa = "rv64imafdc";
60 clocks = <&clkcfg CLK_CPU>;
61 tlb-split;
62 status = "okay";
63 operating-points = <
64 /* kHz uV */
65 600000 1100000
66 300000 950000
67 150000 750000
68 >;
69 cpu1_intc: interrupt-controller {
70 #interrupt-cells = <1>;
71 compatible = "riscv,cpu-intc";
72 interrupt-controller;
73 };
74 };
75
76 cpu2: cpu@2 {
77 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
78 d-cache-block-size = <64>;
79 d-cache-sets = <64>;
80 d-cache-size = <32768>;
81 d-tlb-sets = <1>;
82 d-tlb-size = <32>;
83 device_type = "cpu";
84 i-cache-block-size = <64>;
85 i-cache-sets = <64>;
86 i-cache-size = <32768>;
87 i-tlb-sets = <1>;
88 i-tlb-size = <32>;
89 mmu-type = "riscv,sv39";
90 reg = <2>;
91 riscv,isa = "rv64imafdc";
92 clocks = <&clkcfg CLK_CPU>;
93 tlb-split;
94 status = "okay";
95 operating-points = <
96 /* kHz uV */
97 600000 1100000
98 300000 950000
99 150000 750000
100 >;
101 cpu2_intc: interrupt-controller {
102 #interrupt-cells = <1>;
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 };
106 };
107
108 cpu3: cpu@3 {
109 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
110 d-cache-block-size = <64>;
111 d-cache-sets = <64>;
112 d-cache-size = <32768>;
113 d-tlb-sets = <1>;
114 d-tlb-size = <32>;
115 device_type = "cpu";
116 i-cache-block-size = <64>;
117 i-cache-sets = <64>;
118 i-cache-size = <32768>;
119 i-tlb-sets = <1>;
120 i-tlb-size = <32>;
121 mmu-type = "riscv,sv39";
122 reg = <3>;
123 riscv,isa = "rv64imafdc";
124 clocks = <&clkcfg CLK_CPU>;
125 tlb-split;
126 status = "okay";
127 operating-points = <
128 /* kHz uV */
129 600000 1100000
130 300000 950000
131 150000 750000
132 >;
133 cpu3_intc: interrupt-controller {
134 #interrupt-cells = <1>;
135 compatible = "riscv,cpu-intc";
136 interrupt-controller;
137 };
138 };
139
140 cpu4: cpu@4 {
141 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
142 d-cache-block-size = <64>;
143 d-cache-sets = <64>;
144 d-cache-size = <32768>;
145 d-tlb-sets = <1>;
146 d-tlb-size = <32>;
147 device_type = "cpu";
148 i-cache-block-size = <64>;
149 i-cache-sets = <64>;
150 i-cache-size = <32768>;
151 i-tlb-sets = <1>;
152 i-tlb-size = <32>;
153 mmu-type = "riscv,sv39";
154 reg = <4>;
155 riscv,isa = "rv64imafdc";
156 clocks = <&clkcfg CLK_CPU>;
157 tlb-split;
158 status = "okay";
159 operating-points = <
160 /* kHz uV */
161 600000 1100000
162 300000 950000
163 150000 750000
164 >;
165 cpu4_intc: interrupt-controller {
166 #interrupt-cells = <1>;
167 compatible = "riscv,cpu-intc";
168 interrupt-controller;
169 };
170 };
171 };
172
173 soc {
174 #address-cells = <2>;
175 #size-cells = <2>;
176 compatible = "microchip,mpfs-soc", "simple-bus";
177 ranges;
178
179 clint: clint@2000000 {
180 compatible = "sifive,clint0";
181 reg = <0x0 0x2000000 0x0 0xC000>;
182 interrupts-extended =
183 <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
184 &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
185 &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
186 &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
187 &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
188 };
189
190 cachecontroller: cache-controller@2010000 {
191 compatible = "sifive,fu540-c000-ccache", "cache";
192 reg = <0x0 0x2010000 0x0 0x1000>;
193 interrupt-parent = <&plic>;
194 interrupts = <PLIC_INT_L2_METADATA_CORR
195 PLIC_INT_L2_METADATA_UNCORR
196 PLIC_INT_L2_DATA_CORR>;
197 cache-block-size = <64>;
198 cache-level = <2>;
199 cache-sets = <1024>;
200 cache-size = <2097152>;
201 cache-unified;
202 };
203
204 pdma: pdma@3000000 {
205 compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
206 reg = <0x0 0x3000000 0x0 0x8000>;
207 interrupt-parent = <&plic>;
208 interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
209 PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
210 PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
211 PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
212 #dma-cells = <1>;
213 };
214
215 plic: interrupt-controller@c000000 {
216 compatible = "sifive,plic-1.0.0";
217 reg = <0x0 0xc000000 0x0 0x4000000>;
218 #interrupt-cells = <1>;
219 riscv,ndev = <186>;
220 interrupt-controller;
221 interrupts-extended = <&cpu0_intc HART_INT_M_EXT
222 &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
223 &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
224 &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
225 &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
226 };
227
228 refclk: refclk {
229 compatible = "fixed-clock";
230 #clock-cells = <0>;
231 clock-frequency = <600000000>;
232 clock-output-names = "msspllclk";
233 };
234
235 clkcfg: clkcfg@20002000 {
236 compatible = "microchip,mpfs-clkcfg";
237 reg = <0x0 0x20002000 0x0 0x1000>;
238 reg-names = "mss_sysreg";
239 clocks = <&refclk>;
240 #clock-cells = <1>;
241 clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
242 "mac0", "mac1", "mmc", "timer", /* 4-7 */
243 "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
244 "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
245 "i2c1", "can0", "can1", "usb", /* 16-19 */
246 "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
247 "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
248 "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
249 };
250
251 /* Common node entry for eMMC/SD */
252 mmc: mmc@20008000 {
253 compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
254 reg = <0x0 0x20008000 0x0 0x1000>;
255 clocks = <&clkcfg CLK_MMC>;
256 interrupt-parent = <&plic>;
257 interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
258 max-frequency = <200000000>;
259 status = "disabled";
260 };
261
262 uart0: serial@20000000 {
263 compatible = "ns16550a";
264 reg = <0x0 0x20000000 0x0 0x400>;
265 reg-io-width = <4>;
266 reg-shift = <2>;
267 interrupt-parent = <&plic>;
268 interrupts = <PLIC_INT_MMUART0>;
269 clocks = <&clkcfg CLK_MMUART0>;
270 status = "disabled"; /* Reserved for the HSS */
271 };
272
273 uart1: serial@20100000 {
274 compatible = "ns16550a";
275 reg = <0x0 0x20100000 0x0 0x400>;
276 reg-io-width = <4>;
277 reg-shift = <2>;
278 interrupt-parent = <&plic>;
279 interrupts = <PLIC_INT_MMUART1>;
280 clocks = <&clkcfg CLK_MMUART1>;
281 status = "disabled";
282 };
283
284 uart2: serial@20102000 {
285 compatible = "ns16550a";
286 reg = <0x0 0x20102000 0x0 0x400>;
287 reg-io-width = <4>;
288 reg-shift = <2>;
289 interrupt-parent = <&plic>;
290 interrupts = <PLIC_INT_MMUART2>;
291 clocks = <&clkcfg CLK_MMUART2>;
292 status = "disabled";
293 };
294
295 uart3: serial@20104000 {
296 compatible = "ns16550a";
297 reg = <0x0 0x20104000 0x0 0x400>;
298 reg-io-width = <4>;
299 reg-shift = <2>;
300 interrupt-parent = <&plic>;
301 interrupts = <PLIC_INT_MMUART3>;
302 clocks = <&clkcfg CLK_MMUART3>;
303 status = "disabled";
304 };
305
306 uart4: serial@20106000 {
307 compatible = "ns16550a";
308 reg = <0x0 0x20106000 0x0 0x400>;
309 reg-io-width = <4>;
310 reg-shift = <2>;
311 interrupt-parent = <&plic>;
312 interrupts = <PLIC_INT_MMUART4>;
313 clocks = <&clkcfg CLK_MMUART4>;
314 status = "disabled";
315 };
316
317 spi0: spi@20108000 {
318 compatible = "microchip,mpfs-spi";
319 reg = <0x0 0x20108000 0x0 0x1000>;
320 clocks = <&clkcfg CLK_SPI0>;
321 interrupt-parent = <&plic>;
322 interrupts = <PLIC_INT_SPI0>;
323 num-cs = <8>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
329 spi1: spi@20109000 {
330 compatible = "microchip,mpfs-spi";
331 reg = <0x0 0x20109000 0x0 0x1000>;
332 clocks = <&clkcfg CLK_SPI1>;
333 interrupt-parent = <&plic>;
334 interrupts = <PLIC_INT_SPI1>;
335 num-cs = <8>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339 };
340
341 i2c0: i2c@2010a000 {
342 compatible = "microchip,mpfs-i2c";
343 reg = <0x0 0x2010a000 0x0 0x1000>;
344 clocks = <&clkcfg CLK_I2C0>;
345 interrupt-parent = <&plic>;
346 interrupts = <PLIC_INT_I2C0_MAIN>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 status = "disabled";
350 };
351
352 i2c1: i2c@2010b000 {
353 compatible = "microchip,mpfs-i2c";
354 reg = <0x0 0x2010b000 0x0 0x1000>;
355 clocks = <&clkcfg CLK_I2C1>;
356 interrupt-parent = <&plic>;
357 interrupts = <PLIC_INT_I2C1_MAIN>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
363 can0: can@2010c000 {
364 compatible = "microchip,mpfs-can-uio";
365 reg = <0x0 0x2010c000 0x0 0x1000>;
366 clocks = <&clkcfg CLK_CAN0>;
367 interrupt-parent = <&plic>;
368 interrupts = <PLIC_INT_CAN0>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
374 can1: can@2010d000 {
375 compatible = "microchip,mpfs-can-uio";
376 reg = <0x0 0x2010d000 0x0 0x1000>;
377 clocks = <&clkcfg CLK_CAN1>;
378 interrupt-parent = <&plic>;
379 interrupts = <PLIC_INT_CAN1>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
384
385 mac0: ethernet@20110000 {
386 compatible = "cdns,macb";
387 reg = <0x0 0x20110000 0x0 0x2000>;
388 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
389 clock-names = "pclk", "hclk";
390 interrupt-parent = <&plic>;
391 interrupts = <PLIC_INT_MAC0_INT
392 PLIC_INT_MAC0_QUEUE1
393 PLIC_INT_MAC0_QUEUE2
394 PLIC_INT_MAC0_QUEUE3
395 PLIC_INT_MAC0_EMAC
396 PLIC_INT_MAC0_MMSL>;
397 local-mac-address = [00 00 00 00 00 00];
398 status = "disabled";
399 #address-cells = <1>;
400 #size-cells = <0>;
401 };
402
403 mac1: ethernet@20112000 {
404 compatible = "cdns,macb";
405 reg = <0x0 0x20112000 0x0 0x2000>;
406 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
407 clock-names = "pclk", "hclk";
408 interrupt-parent = <&plic>;
409 interrupts = <PLIC_INT_MAC1_INT
410 PLIC_INT_MAC1_QUEUE1
411 PLIC_INT_MAC1_QUEUE2
412 PLIC_INT_MAC1_QUEUE3
413 PLIC_INT_MAC1_EMAC
414 PLIC_INT_MAC1_MMSL>;
415 local-mac-address = [00 00 00 00 00 00];
416 status = "disabled";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
420
421 gpio0: gpio@20120000 {
422 compatible = "microchip,mpfs-gpio";
423 reg = <0x0 0x20120000 0x0 0x1000>;
424 reg-names = "control";
425 clocks = <&clkcfg CLK_GPIO0>;
426 interrupt-parent = <&plic>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 status = "disabled";
430 };
431
432 gpio1: gpio@20121000 {
433 compatible = "microchip,mpfs-gpio";
434 reg = <000 0x20121000 0x0 0x1000>;
435 reg-names = "control";
436 clocks = <&clkcfg CLK_GPIO1>;
437 interrupt-parent = <&plic>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 status = "disabled";
441 };
442
443 gpio2: gpio@20122000 {
444 compatible = "microchip,mpfs-gpio";
445 reg = <0x0 0x20122000 0x0 0x1000>;
446 reg-names = "control";
447 clocks = <&clkcfg CLK_GPIO2>;
448 interrupt-parent = <&plic>;
449 gpio-controller;
450 #gpio-cells = <2>;
451 status = "disabled";
452 };
453
454 rtc: rtc@20124000 {
455 compatible = "microchip,mpfs-rtc";
456 reg = <0x0 0x20124000 0x0 0x1000>;
457 clocks = <&clkcfg CLK_RTC>;
458 clock-names = "rtc";
459 interrupt-parent = <&plic>;
460 interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
465
466 usb: usb@20201000 {
467 compatible = "microchip,mpfs-usb-host";
468 reg = <0x0 0x20201000 0x0 0x1000>;
469 reg-names = "mc","control";
470 clocks = <&clkcfg CLK_USB>;
471 interrupt-parent = <&plic>;
472 interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
473 interrupt-names = "dma","mc";
474 dr_mode = "host";
475 status = "disabled";
476 };
477
478 qspi: qspi@21000000 {
479 compatible = "microchip,mpfs-qspi";
480 reg = <0x0 0x21000000 0x0 0x1000>;
481 clocks = <&clkcfg CLK_QSPI>;
482 interrupt-parent = <&plic>;
483 interrupts = <PLIC_INT_QSPI>;
484 num-cs = <8>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 status = "disabled";
488 };
489
490 mbox: mailbox@37020000 {
491 compatible = "microchip,mpfs-mailbox";
492 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
493 interrupt-parent = <&plic>;
494 interrupts = <PLIC_INT_G5C_MESSAGE>;
495 #mbox-cells = <1>;
496 status = "disabled";
497 };
498
499 pcie: pcie@2000000000 {
500 compatible = "microchip,pcie-host-1.0";
501 #address-cells = <0x3>;
502 #interrupt-cells = <0x1>;
503 #size-cells = <0x2>;
504 device_type = "pci";
505 reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
506 reg-names = "cfg", "apb";
507 clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
508 clock-names = "fic0", "fic1", "fic3";
509 bus-range = <0x0 0x7f>;
510 interrupt-parent = <&plic>;
511 interrupts = <PLIC_INT_FABRIC_F2H_2>;
512 interrupt-map = <0 0 0 1 &pcie_intc 0>,
513 <0 0 0 2 &pcie_intc 1>,
514 <0 0 0 3 &pcie_intc 2>,
515 <0 0 0 4 &pcie_intc 3>;
516 interrupt-map-mask = <0 0 0 7>;
517 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
518 msi-parent = <&pcie>;
519 msi-controller;
520 mchp,axi-m-atr0 = <0x10 0x0>;
521 status = "disabled";
522 pcie_intc: legacy-interrupt-controller {
523 #address-cells = <0>;
524 #interrupt-cells = <1>;
525 interrupt-controller;
526 };
527 };
528
529 syscontroller: syscontroller {
530 compatible = "microchip,mpfs-sys-controller";
531 #address-cells = <1>;
532 #size-cells = <1>;
533 mboxes = <&mbox 0>;
534 };
535
536 hwrandom: hwrandom {
537 compatible = "microchip,mpfs-rng";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 syscontroller = <&syscontroller>;
541 };
542
543 serialnum: serialnum {
544 compatible = "microchip,mpfs-serial-number";
545 #address-cells = <1>;
546 #size-cells = <1>;
547 syscontroller = <&syscontroller>;
548 };
549
550 fpgadigest: fpgadigest {
551 compatible = "microchip,mpfs-digest";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 syscontroller = <&syscontroller>;
555 };
556
557 devicecert: cert {
558 compatible = "microchip,mpfs-device-cert";
559 #address-cells = <1>;
560 #size-cells = <1>;
561 syscontroller = <&syscontroller>;
562 };
563
564 signature: signature {
565 compatible = "microchip,mpfs-signature";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 syscontroller = <&syscontroller>;
569 };
570 };
571};