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git01.mediatek.com / filogic / uboot / 9668b8772fa8c2013bef043f2870bf1c2869af39 / . / arch / arm / dts / t8103.dtsi
blob: 03d8436fece20bdfcc1c623390da1c80f3848b4b [file] [log] [blame]
Mark Kettenis2ec941f2021-10-23 16:58:06 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple T8103 "M1" SoC
4 *
5 * Other names: H13G, "Tonga"
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/apple-aic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/apple.h>
14#include <dt-bindings/spmi/spmi.h>
15
16/ {
17 compatible = "apple,t8103", "apple,arm-platform";
18
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 compatible = "apple,icestorm";
28 device_type = "cpu";
29 reg = <0x0 0x0>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0 0>; /* To be filled by loader */
32 };
33
34 cpu1: cpu@1 {
35 compatible = "apple,icestorm";
36 device_type = "cpu";
37 reg = <0x0 0x1>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0 0>; /* To be filled by loader */
40 };
41
42 cpu2: cpu@2 {
43 compatible = "apple,icestorm";
44 device_type = "cpu";
45 reg = <0x0 0x2>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0 0>; /* To be filled by loader */
48 };
49
50 cpu3: cpu@3 {
51 compatible = "apple,icestorm";
52 device_type = "cpu";
53 reg = <0x0 0x3>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0 0>; /* To be filled by loader */
56 };
57
58 cpu4: cpu@10100 {
59 compatible = "apple,firestorm";
60 device_type = "cpu";
61 reg = <0x0 0x10100>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 };
65
66 cpu5: cpu@10101 {
67 compatible = "apple,firestorm";
68 device_type = "cpu";
69 reg = <0x0 0x10101>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0 0>; /* To be filled by loader */
72 };
73
74 cpu6: cpu@10102 {
75 compatible = "apple,firestorm";
76 device_type = "cpu";
77 reg = <0x0 0x10102>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0 0>; /* To be filled by loader */
80 };
81
82 cpu7: cpu@10103 {
83 compatible = "apple,firestorm";
84 device_type = "cpu";
85 reg = <0x0 0x10103>;
86 enable-method = "spin-table";
87 cpu-release-addr = <0 0>; /* To be filled by loader */
88 };
89 };
90
91 timer {
92 compatible = "arm,armv8-timer";
93 interrupt-parent = <&aic>;
94 interrupt-names = "hyp-phys", "hyp-virt", "phys", "virt";
95 interrupts = <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
96 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>,
97 <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
98 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
99 };
100
101 clkref: clock-ref {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <24000000>;
105 clock-output-names = "clkref";
106 };
107
108 soc {
109 compatible = "simple-bus";
110 #address-cells = <2>;
111 #size-cells = <2>;
112
113 ranges;
114 dma-ranges;
115 dma-coherent;
116 nonposted-mmio;
117
118 serial0: serial@235200000 {
119 compatible = "apple,s5l-uart";
120 reg = <0x2 0x35200000 0x0 0x1000>;
121 reg-io-width = <4>;
122 interrupt-parent = <&aic>;
123 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&clkref>, <&clkref>, <&clkref>;
125 clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1";
126 power-domains = <&ps_uart0>;
127 status = "disabled";
128 };
129
130 serial2: serial@235208000 {
131 compatible = "apple,s5l-uart";
132 reg = <0x2 0x35208000 0x0 0x1000>;
133 reg-io-width = <4>;
134 interrupt-parent = <&aic>;
135 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clkref>, <&clkref>, <&clkref>;
137 clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1";
138 power-domains = <&ps_uart2>;
139 status = "disabled";
140 };
141
142 aic: interrupt-controller@23b100000 {
143 compatible = "apple,t8103-aic", "apple,aic";
144 #interrupt-cells = <3>;
145 interrupt-controller;
146 reg = <0x2 0x3b100000 0x0 0x8000>;
147 };
148
149 pmgr: power-controller@23b700000 {
150 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 reg = <0x2 0x3b700000 0x0 0x14000>;
155
156 ps_pcie_ref: power-controller@1a0 {
157 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
158 reg = <0x1a0>;
159 #power-domain-cells = <0>;
160 #reset-cells = <0>;
161 apple,domain-name = "pcie_ref";
162 };
163
164 ps_imx: power-controller@1b8 {
165 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
166 reg = <0x1b8>;
167 #power-domain-cells = <0>;
168 #reset-cells = <0>;
169 apple,domain-name = "imx";
170 apple,always-on;
171 };
172
173 ps_sio: power-controller@1c0 {
174 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
175 reg = <0x1c0>;
176 #power-domain-cells = <0>;
177 #reset-cells = <0>;
178 apple,domain-name = "sio";
179 };
180
181 ps_uart_p: power-controller@220 {
182 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
183 reg = <0x220>;
184 #power-domain-cells = <0>;
185 #reset-cells = <0>;
186 power-domains = <&ps_sio>;
187 apple,domain-name = "uart_p";
188 };
189
190 ps_uart0: power-controller@270 {
191 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
192 reg = <0x270>;
193 #power-domain-cells = <0>;
194 #reset-cells = <0>;
195 power-domains = <&ps_uart_p>;
196 apple,domain-name = "uart0";
197 };
198
199 ps_uart1: power-controller@278 {
200 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
201 reg = <0x278>;
202 #power-domain-cells = <0>;
203 #reset-cells = <0>;
204 apple,domain-name = "uart1";
205 power-domains = <&ps_uart_p>;
206 };
207
208 ps_uart2: power-controller@280 {
209 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
210 reg = <0x280>;
211 #power-domain-cells = <0>;
212 #reset-cells = <0>;
213 apple,domain-name = "uart2";
214 power-domains = <&ps_uart_p>;
215 };
216
217 ps_uart3: power-controller@288 {
218 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
219 reg = <0x288>;
220 #power-domain-cells = <0>;
221 #reset-cells = <0>;
222 apple,domain-name = "uart3";
223 power-domains = <&ps_uart_p>;
224 };
225
226 ps_apcie: power-controller@348 {
227 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
228 reg = <0x348>;
229 #power-domain-cells = <0>;
230 #reset-cells = <0>;
231 apple,domain-name = "apcie";
232 power-domains = <&ps_imx>;
233 };
234
235 ps_apcie_gp: power-controller@3e8 {
236 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
237 reg = <0x3e8>;
238 #power-domain-cells = <0>;
239 #reset-cells = <0>;
240 apple,domain-name = "apcie_gp";
241 power-domains = <&ps_apcie>;
242 };
243
244 ps_ans2: power-controller@3f0 {
245 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
246 reg = <0x3f0>;
247 #power-domain-cells = <0>;
248 #reset-cells = <0>;
249 apple,domain-name = "ans2";
250 power-domains = <&ps_apcie_st>;
251 };
252
253 ps_apcie_st: power-controller@418 {
254 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
255 reg = <0x418>;
256 #power-domain-cells = <0>;
257 #reset-cells = <0>;
258 apple,domain-name = "apcie_st";
259 power-domains = <&ps_apcie>;
260 };
261 };
262
263 pinctrl_ap: pinctrl@23c100000 {
264 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
265 reg = <0x2 0x3c100000 0x0 0x100000>;
266
267 gpio-controller;
268 #gpio-cells = <2>;
269 gpio-ranges = <&pinctrl_ap 0 0 212>;
270
271 interrupt-controller;
272 interrupt-parent = <&aic>;
273 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
274 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
275 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
276 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
277 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
278 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
279 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
280
281 i2c0_pins: i2c0_pins {
282 pinmux = <APPLE_PINMUX(188, 1)>,
283 <APPLE_PINMUX(192, 1)>;
284 };
285
286 pcie_pins: pcie-pins {
287 pinmux = <APPLE_PINMUX(150, 1)>,
288 <APPLE_PINMUX(151, 1)>,
289 <APPLE_PINMUX(32, 1)>;
290 };
291 };
292
293 pinctrl_aop: pinctrl@24a820000 {
294 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
295 reg = <0x2 0x4a820000 0x0 0x4000>;
296
297 gpio-controller;
298 #gpio-cells = <2>;
299 gpio-ranges = <&pinctrl_aop 0 0 42>;
300
301 interrupt-controller;
302 interrupt-parent = <&aic>;
303 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
304 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
305 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
306 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
307 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
308 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
309 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
310 };
311
312 pinctrl_nub: pinctrl@23d1f0000 {
313 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
314 reg = <0x2 0x3d1f0000 0x0 0x4000>;
315
316 gpio-controller;
317 #gpio-cells = <2>;
318 gpio-ranges = <&pinctrl_nub 0 0 23>;
319
320 interrupt-controller;
321 interrupt-parent = <&aic>;
322 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
323 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
324 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
325 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
326 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
327 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
328 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
329 };
330
Mark Kettenisfb646142022-01-12 19:55:16 +0100[diff] [blame]331 wdt: watchdog@23d2b0000 {
332 compatible = "apple,t8103-wdt", "apple,wdt";
333 reg = <0x2 0x3d2b0000 0x0 0x4000>;
334 clocks = <&clkref>;
335 interrupt-parent = <&aic>;
336 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>;
337 };
338
Mark Kettenis2ec941f2021-10-23 16:58:06 +0200[diff] [blame]339 pinctrl_smc: pinctrl@23e820000 {
340 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
341 reg = <0x2 0x3e820000 0x0 0x4000>;
342
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pinctrl_smc 0 0 16>;
346
347 interrupt-controller;
348 interrupt-parent = <&aic>;
349 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
350 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
351 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
352 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
353 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
354 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
355 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
356 };
357
358 i2c0: i2c@20a110000 {
359 compatible = "apple,i2c-v0";
360 reg = <0x2 0x35010000 0x0 0x4000>;
361 interrupt-parent = <&aic>;
362 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clkref>;
364 pinctrl-0 = <&i2c0_pins>;
365 pinctrl-names = "default";
366 #address-cells = <0x1>;
367 #size-cells = <0x0>;
368
369 hpm0: hpm@38 {
370 compatible = "ti,tps6598x";
371 reg = <0x38>;
372 };
373
374 hpm1: hpm@3f {
375 compatible = "ti,tps6598x";
376 reg = <0x3f>;
377 };
378 };
379
380 ans_mbox: mbox@277400000 {
381 compatible = "apple,iop-mailbox-m1";
382 reg = <0x2 0x77400000 0x0 0x20000>;
383 interrupt-parent = <&aic>;
384 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
385 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
386 power-domains = <&ps_ans2>;
387 #mbox-cells = <1>;
388 endpoints = <32>;
389 };
390
391 ans@27bcc0000 {
392 compatible = "apple,nvme-m1";
393 reg = <0x2 0x7bcc0000 0x0 0x40000>,
394 <0x2 0x7bc50000 0x0 0x4000>;
395 interrupt-parent = <&aic>;
396 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
397 power-domains = <&ps_apcie_st>;
398 mboxes = <&ans_mbox 32>;
399 };
400
401 pcie0_dart_0: iommu@681008000 {
402 compatible = "apple,t8103-dart", "apple,dart-m1";
403 reg = <0x6 0x81008000 0x0 0x4000>;
404 interrupt-parent = <&aic>;
405 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
406 #iommu-cells = <1>;
407 status = "disabled";
408 };
409
410 pcie0_dart_1: iommu@682008000 {
411 compatible = "apple,t8103-dart", "apple,dart-m1";
412 reg = <0x6 0x82008000 0x0 0x4000>;
413 interrupt-parent = <&aic>;
414 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
415 #iommu-cells = <1>;
416 status = "disabled";
417 };
418
419 pcie0_dart_2: iommu@683008000 {
420 compatible = "apple,t8103-dart", "apple,dart-m1";
421 reg = <0x6 0x83008000 0x0 0x4000>;
422 interrupt-parent = <&aic>;
423 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
424 #iommu-cells = <1>;
425 status = "disabled";
426 };
427
428 smc_mbox: mbox@23e400000 {
429 compatible = "apple,iop-mailbox-m1";
430 reg = <0x2 0x3e400000 0x0 0x20000>;
431 #mbox-cells = <1>;
432 endpoints = <32>;
433 };
434
435 smc: smc@23e050000 {
436 compatible = "apple,smc-m1";
437 reg = <0x2 0x3e050000 0x0 0x4000>;
438 mboxes = <&smc_mbox 32>;
439 gpio-controller;
440 #gpio-cells = <2>;
441 gpio-13 = <0x00800000>;
442 };
443
444 pcie0: pcie@690000000 {
445 compatible = "apple,t8103-pcie", "apple,pcie";
446
447 reg = <0x6 0x90000000 0x0 0x1000000>,
448 <0x6 0x80000000 0x0 0x4000>,
449 <0x6 0x81000000 0x0 0x8000>,
450 <0x6 0x82000000 0x0 0x8000>,
451 <0x6 0x83000000 0x0 0x8000>;
452 reg-names = "config", "rc", "port0", "port1", "port2";
453
454 interrupt-parent = <&aic>;
455 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
456 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
457 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
458
459 msi-controller;
460 msi-parent = <&pcie0>;
461 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
462
463 iommu-map = <0x100 &pcie0_dart_0 1 1>,
464 <0x200 &pcie0_dart_1 1 1>,
465 <0x300 &pcie0_dart_2 1 1>;
466 iommu-map-mask = <0xff00>;
467
468 bus-range = <0 3>;
469 #address-cells = <3>;
470 #size-cells = <2>;
471 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000
472 0x0 0x20000000>,
473 <0x02000000 0x0 0xc0000000 0x6 0xc0000000
474 0x0 0x40000000>;
475
476 power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>;
477 pinctrl-0 = <&pcie_pins>;
478 pinctrl-names = "default";
479
480 device_type = "pci";
481 status = "disabled";
482 };
483
484 dwc3_0_dart_0: iommu@382f00000 {
485 compatible = "apple,t8103-dart";
486 reg = <0x3 0x82f00000 0x0 0x4000>;
487 interrupt-parent = <&aic>;
488 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
489 #iommu-cells = <1>;
490 status = "disabled";
491 };
492
493 dwc3_0_dart_1: iommu@382f80000 {
494 compatible = "apple,t8103-dart";
495 reg = <0x3 0x82f80000 0x0 0x4000>;
496 interrupt-parent = <&aic>;
497 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
498 #iommu-cells = <1>;
499 status = "disabled";
500 };
501
502 dwc3_0: usb@382280000{
503 compatible = "snps,dwc3";
504 reg = <0x3 0x82280000 0x0 0x100000>;
505 interrupt-parent = <&aic>;
506 interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
507 dr_mode = "host";
508 iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
509 status = "disabled";
510 };
511
512 dwc3_1_dart_0: iommu@502f00000 {
513 compatible = "apple,t8103-dart";
514 reg = <0x5 0x02f00000 0x0 0x4000>;
515 interrupt-parent = <&aic>;
516 interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
517 #iommu-cells = <1>;
518 status = "disabled";
519 };
520
521 dwc3_1_dart_1: iommu@502f80000 {
522 compatible = "apple,t8103-dart";
523 reg = <0x5 0x02f80000 0x0 0x4000>;
524 interrupt-parent = <&aic>;
525 interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
526 #iommu-cells = <1>;
527 status = "disabled";
528 };
529
530 dwc3_1: usb@502280000{
531 compatible = "snps,dwc3";
532 reg = <0x5 0x02280000 0x0 0x100000>;
533 interrupt-parent = <&aic>;
534 interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
535 dr_mode = "host";
536 iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
537 status = "disabled";
538 };
539
Mark Kettenis2ec941f2021-10-23 16:58:06 +0200[diff] [blame]540 spi@23510c000 {
541 compatible = "apple,t8103-spi", "apple,spi";
542 reg = <0x2 0x3510c000 0x0 0x4000>;
543 interrupt-parent = <&aic>;
544 interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>;
545 cs-gpios = <&pinctrl_ap 49 GPIO_ACTIVE_HIGH>;
546 };
547
548 spmi@23d0d8000 {
549 compatible = "apple,t8103-spmi", "apple,spmi";
550 reg = <0x2 0x3d0d9300 0x0 0x100>;
551 interrupt-parent = <&aic>;
552 interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>;
553
554 #address-cells = <2>;
555 #size-cells = <0>;
556
557 pmu@f {
558 compatible = "apple,sera-pmu";
559 reg = <0xf SPMI_USID>;
560 };
561 };
562 };
563};