| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Texas Instruments Incorporated, <www.ti.com> |
| 5 | * |
| 6 | * Balaji Krishnamoorthy <balajitk@ti.com> |
| 7 | * Aneesh V <aneesh@ti.com> |
| Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 8 | */ |
| Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 9 | #ifndef _SDP4430_MUX_DATA_H |
| 10 | #define _SDP4430_MUX_DATA_H |
| Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 11 | |
| Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 12 | #include <asm/arch/mux_omap4.h> |
| 13 | |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 14 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 15 | |
| 16 | {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ |
| 17 | {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ |
| 18 | {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ |
| 19 | {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ |
| 20 | {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ |
| 21 | {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ |
| 22 | {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ |
| 23 | {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ |
| 24 | {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ |
| 25 | {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ |
| 26 | {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
| 27 | {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
| 28 | {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
| 29 | {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
| 30 | {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
| 31 | {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
| 32 | {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ |
| 33 | {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ |
| 34 | {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ |
| 35 | {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 36 | {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
| 37 | {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
| 38 | {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ |
| SRICHARAN R | 264a06c | 2012-06-12 19:53:32 +0000 | [diff] [blame] | 39 | {UART3_TX_IRTX, (M0)}, /* uart3_tx */ |
| 40 | {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
| 41 | {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
| 42 | {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
| 43 | {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
| 44 | {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ |
| 45 | {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ |
| 46 | {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ |
| 47 | {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ |
| 48 | {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
| 49 | {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
| 50 | {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | const struct pad_conf_entry wkup_padconf_array_essential[] = { |
| 54 | |
| 55 | {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
| 56 | {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
| 57 | {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ |
| 58 | |
| 59 | }; |
| 60 | |
| 61 | const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { |
| 62 | |
| Nishanth Menon | a0f45c1 | 2012-03-01 14:17:38 +0000 | [diff] [blame] | 63 | {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 64 | |
| 65 | }; |
| 66 | |
| Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 67 | #endif /* _SDP4430_MUX_DATA_H */ |