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git01.mediatek.com / filogic / uboot / 9602661ec85c31ac91ea9ec6fd7d2ebe5f3e402f / . / arch / x86 / cpu / sc520 / sc520_ssi.c
blob: cc601e56e48328e8998c3e47b4beb229f7779a39 [file] [log] [blame]
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]1/*
2 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]3 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]24#include <common.h>
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]25#include <asm/io.h>
Graeme Russ0d992d02011-08-04 22:05:09 +1000[diff] [blame]26#include <asm/arch/ssi.h>
27#include <asm/arch/sc520.h>
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]28
29int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
30{
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]31 u8 temp = 0;
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]32
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]33 if (freq >= 8192)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]34 temp |= CTL_CLK_SEL_4;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]35 else if (freq >= 4096)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]36 temp |= CTL_CLK_SEL_8;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]37 else if (freq >= 2048)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]38 temp |= CTL_CLK_SEL_16;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]39 else if (freq >= 1024)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]40 temp |= CTL_CLK_SEL_32;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]41 else if (freq >= 512)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]42 temp |= CTL_CLK_SEL_64;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]43 else if (freq >= 256)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]44 temp |= CTL_CLK_SEL_128;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]45 else if (freq >= 128)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]46 temp |= CTL_CLK_SEL_256;
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]47 else
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]48 temp |= CTL_CLK_SEL_512;
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]49
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]50 if (!lsb_first)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]51 temp |= MSBF_ENB;
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]52
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]53 if (inv_clock)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]54 temp |= CLK_INV_ENB;
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]55
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]56 if (inv_phase)
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]57 temp |= PHS_INV_ENB;
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]58
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]59 writeb(temp, &sc520_mmcr->ssictl);
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]60
61 return 0;
62}
63
64u8 ssi_txrx_byte(u8 data)
65{
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]66 writeb(data, &sc520_mmcr->ssixmit);
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]67 while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
68 ;
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]69 writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]70 while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
71 ;
Graeme Russ1d977dc2009-08-23 12:59:56 +1000[diff] [blame]72
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]73 return readb(&sc520_mmcr->ssircv);
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]74}
75
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]76void ssi_tx_byte(u8 data)
77{
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]78 writeb(data, &sc520_mmcr->ssixmit);
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]79 while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
80 ;
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]81 writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]82}
83
84u8 ssi_rx_byte(void)
85{
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]86 while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
87 ;
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]88 writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
Graeme Russ55bed242011-11-08 02:33:14 +0000[diff] [blame]89 while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
90 ;
Graeme Russ1d977dc2009-08-23 12:59:56 +1000[diff] [blame]91
Graeme Russ0c5ced72010-04-24 00:05:37 +1000[diff] [blame]92 return readb(&sc520_mmcr->ssircv);
Graeme Russ85cc39f2009-02-24 21:14:32 +1100[diff] [blame]93}