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git01.mediatek.com / filogic / uboot / 95fc6d6dbe280de855fcfdef6df10844dd7b3c72 / . / arch / arm / cpu / u-boot.lds
blob: 9463a33dcb3dab4b99f558b5774a25787df9486f [file] [log] [blame]
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]1/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]8 */
9
10OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
11OUTPUT_ARCH(arm)
12ENTRY(_start)
13SECTIONS
14{
15 . = 0x00000000;
16
17 . = ALIGN(4);
18 .text :
19 {
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]20 *(.__image_copy_start)
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]21 CPUDIR/start.o (.text*)
22 *(.text*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]23 }
24
25 . = ALIGN(4);
26 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
27
28 . = ALIGN(4);
29 .data : {
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]30 *(.data*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]31 }
32
33 . = ALIGN(4);
34
35 . = .;
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]36
37 . = ALIGN(4);
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]38 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]39 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]40 }
41
42 . = ALIGN(4);
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]43
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]44 .image_copy_end :
45 {
46 *(.__image_copy_end)
47 }
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]48
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]49 .rel_dyn_start :
50 {
51 *(.__rel_dyn_start)
52 }
53
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]54 .rel.dyn : {
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]55 *(.rel*)
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]56 }
57
58 .rel_dyn_end :
59 {
60 *(.__rel_dyn_end)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]61 }
62
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]63 _end = .;
64
65 /*
66 * Deprecated: this MMU section is used by pxa at present but
67 * should not be used by new boards/CPUs.
68 */
69 . = ALIGN(4096);
70 .mmutable : {
71 *(.mmutable)
72 }
73
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]74/*
75 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
76 * __bss_base and __bss_limit are for linker only (overlay ordering)
77 */
78
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]79 .bss_start __rel_dyn_start (OVERLAY) : {
80 KEEP(*(.__bss_start));
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]81 __bss_base = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]82 }
83
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]84 .bss __bss_base (OVERLAY) : {
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]85 *(.bss*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]86 . = ALIGN(4);
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]87 __bss_limit = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]88 }
Tom Rini19aac972013-03-18 12:31:00 -0400[diff] [blame]89
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]90 .bss_end __bss_limit (OVERLAY) : {
91 KEEP(*(.__bss_end));
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]92 }
93
Albert ARIBAUD95fc6d62013-11-07 14:21:46 +0100[diff] [blame^]94 .dynsym _end : { *(.dynsym) }
95 .hash : { *(.hash) }
96 .got.plt : { *(.got.plt) }
97 .dynbss : { *(.dynbss) }
98 .dynstr : { *(.dynstr*) }
99 .dynamic : { *(.dynamic*) }
100 .plt : { *(.plt*) }
101 .interp : { *(.interp*) }
102 .gnu : { *(.gnu*) }
103 .ARM.exidx : { *(.ARM.exidx*) }
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]104}