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git01.mediatek.com / filogic / uboot / 95f6e4b2cb4711b0dd4024f0821a957d0deec1c1 / . / arch / arm / dts / rk356x-u-boot.dtsi
blob: ecf88e084158d1b65db0f4e9282cf98c2a0e7218 [file] [log] [blame]
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &sdhci;
11 mmc1 = &sdmmc0;
12 };
13
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]14 chosen {
15 u-boot,spl-boot-order = &sdhci, &sdmmc0;
16 };
17
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]18 dmc: dmc {
19 compatible = "rockchip,rk3568-dmc";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]21 status = "okay";
22 };
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]23
24 otp: nvmem@fe38c000 {
25 compatible = "rockchip,rk3568-otp";
26 reg = <0x0 0xfe38c000 0x0 0x4000>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 status = "okay";
30
31 cpu_id: id@a {
32 reg = <0x0a 0x10>;
33 };
34 };
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]35};
36
Jagan Tekia79aec32023-02-17 17:28:42 +0530[diff] [blame]37&combphy1 {
38 /delete-property/ assigned-clocks;
39 /delete-property/ assigned-clock-rates;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]40};
41
42&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]44 status = "okay";
45};
46
47&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]49 status = "okay";
50};
51
52&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]54 status = "okay";
55};
56
57&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]59 status = "okay";
60};
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]61
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]62&sdhci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]64 status = "okay";
65};
66
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]67&sdmmc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]69 status = "okay";
70};