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git01.mediatek.com / filogic / uboot / 95ee2aef1789d3bff69290f9035d03fb7b16d8fd / . / board / sbc8641d / law.c
blob: dc4696d123f474e3bde1a2fcef96151f7e8e3043 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]2/*
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]7 */
8
9#include <common.h>
10#include <asm/fsl_law.h>
11#include <asm/mmu.h>
12
13/*
14 * LAW (Local Access Window) configuration:
15 *
16 * 0x0000_0000 DDR 256M
17 * 0x1000_0000 DDR2 256M
Kumar Galae78f6652010-07-09 00:02:34 -0500[diff] [blame]18 * 0x8000_0000 PCIE1 MEM 512M
19 * 0xa000_0000 PCIE2 MEM 512M
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]20 * 0xc000_0000 RapidIO 512M
Kumar Galae78f6652010-07-09 00:02:34 -0500[diff] [blame]21 * 0xe200_0000 PCIE1 IO 16M
22 * 0xe300_0000 PCIE2 IO 16M
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]23 * 0xf800_0000 CCSRBAR 2M
24 * 0xfe00_0000 FLASH (boot bank) 32M
25 *
26 */
27
28
29struct law_entry law_table[] = {
Paul Gortmaker0253f602009-09-30 16:12:31 -0400[diff] [blame]30#if !defined(CONFIG_SPD_EEPROM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]31 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
Paul Gortmaker0253f602009-09-30 16:12:31 -0400[diff] [blame]32 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
33 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
34#endif
Kumar Gala994fdba2008-06-11 00:51:45 -0500[diff] [blame]35 SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
Kumar Gala994fdba2008-06-11 00:51:45 -0500[diff] [blame]36 SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]37};
38
39int num_law_entries = ARRAY_SIZE(law_table);