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git01.mediatek.com / filogic / uboot / 95eb65aead3cc8f4be9c1924597920b4a797619e / . / board / renesas / koelsch / qos.c
blob: e6c5e48df5e521b146c0306c299a7cce3ed51204 [file] [log] [blame]
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1/*
2 * board/renesas/koelsch/qos.c
3 *
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]4 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]5 *
6 * SPDX-License-Identifier: GPL-2.0
7 *
8 */
9
10#include <common.h>
11#include <asm/processor.h>
12#include <asm/mach-types.h>
13#include <asm/io.h>
14#include <asm/arch/rmobile.h>
15
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]16/* QoS version 0.240 for ES1 and version 0.310 for ES2 */
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]17
18enum {
19 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
20 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
21 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
22 DBSC3_15,
23 DBSC3_NR,
24};
25
26static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
27 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
28 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
29 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
30 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
31 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
32 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
33 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
34 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
35 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
36 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
37 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
38 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
39 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
40 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
41 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
42 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
43};
44
45static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
46 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
47 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
48 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
49 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
50 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
51 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
52 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
53 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
54 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
55 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
56 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
57 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
58 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
59 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
60 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
61 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
62};
63
64static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
65 [DBSC3_00] = DBSC3_1_QOS_R0_BASE,
66 [DBSC3_01] = DBSC3_1_QOS_R1_BASE,
67 [DBSC3_02] = DBSC3_1_QOS_R2_BASE,
68 [DBSC3_03] = DBSC3_1_QOS_R3_BASE,
69 [DBSC3_04] = DBSC3_1_QOS_R4_BASE,
70 [DBSC3_05] = DBSC3_1_QOS_R5_BASE,
71 [DBSC3_06] = DBSC3_1_QOS_R6_BASE,
72 [DBSC3_07] = DBSC3_1_QOS_R7_BASE,
73 [DBSC3_08] = DBSC3_1_QOS_R8_BASE,
74 [DBSC3_09] = DBSC3_1_QOS_R9_BASE,
75 [DBSC3_10] = DBSC3_1_QOS_R10_BASE,
76 [DBSC3_11] = DBSC3_1_QOS_R11_BASE,
77 [DBSC3_12] = DBSC3_1_QOS_R12_BASE,
78 [DBSC3_13] = DBSC3_1_QOS_R13_BASE,
79 [DBSC3_14] = DBSC3_1_QOS_R14_BASE,
80 [DBSC3_15] = DBSC3_1_QOS_R15_BASE,
81};
82
83static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
84 [DBSC3_00] = DBSC3_1_QOS_W0_BASE,
85 [DBSC3_01] = DBSC3_1_QOS_W1_BASE,
86 [DBSC3_02] = DBSC3_1_QOS_W2_BASE,
87 [DBSC3_03] = DBSC3_1_QOS_W3_BASE,
88 [DBSC3_04] = DBSC3_1_QOS_W4_BASE,
89 [DBSC3_05] = DBSC3_1_QOS_W5_BASE,
90 [DBSC3_06] = DBSC3_1_QOS_W6_BASE,
91 [DBSC3_07] = DBSC3_1_QOS_W7_BASE,
92 [DBSC3_08] = DBSC3_1_QOS_W8_BASE,
93 [DBSC3_09] = DBSC3_1_QOS_W9_BASE,
94 [DBSC3_10] = DBSC3_1_QOS_W10_BASE,
95 [DBSC3_11] = DBSC3_1_QOS_W11_BASE,
96 [DBSC3_12] = DBSC3_1_QOS_W12_BASE,
97 [DBSC3_13] = DBSC3_1_QOS_W13_BASE,
98 [DBSC3_14] = DBSC3_1_QOS_W14_BASE,
99 [DBSC3_15] = DBSC3_1_QOS_W15_BASE,
100};
101
102void qos_init(void)
103{
104 int i;
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]105 struct rcar_s3c *s3c;
106 struct rcar_s3c_qos *s3c_qos;
107 struct rcar_dbsc3_qos *qos_addr;
108 struct rcar_mxi *mxi;
109 struct rcar_mxi_qos *mxi_qos;
110 struct rcar_axi_qos *axi_qos;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]111
112 /* DBSC DBADJ2 */
113 writel(0x20042004, DBSC3_0_DBADJ2);
114
115 /* S3C -QoS */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]116 s3c = (struct rcar_s3c *)S3C_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]117 if (IS_R8A7791_ES2()) {
118 writel(0x00FF1B0D, &s3c->s3cadsplcr);
119 writel(0x1F0D0B0A, &s3c->s3crorr);
120 writel(0x1F0D0B09, &s3c->s3cworr);
121 writel(0x00200808, &s3c->s3carcr11);
122 } else {
123 writel(0x00FF1B1D, &s3c->s3cadsplcr);
124 writel(0x1F0D0C0C, &s3c->s3crorr);
125 writel(0x1F0D0C0A, &s3c->s3cworr);
126 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]127 /* QoS Control Registers */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]128 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]129 writel(0x00890089, &s3c_qos->s3cqos0);
130 writel(0x20960010, &s3c_qos->s3cqos1);
131 writel(0x20302030, &s3c_qos->s3cqos2);
132 writel(0x20AA2200, &s3c_qos->s3cqos3);
133 writel(0x00002032, &s3c_qos->s3cqos4);
134 writel(0x20960010, &s3c_qos->s3cqos5);
135 writel(0x20302030, &s3c_qos->s3cqos6);
136 writel(0x20AA2200, &s3c_qos->s3cqos7);
137 writel(0x00002032, &s3c_qos->s3cqos8);
138
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]139 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]140 writel(0x00890089, &s3c_qos->s3cqos0);
141 writel(0x20960010, &s3c_qos->s3cqos1);
142 writel(0x20302030, &s3c_qos->s3cqos2);
143 writel(0x20AA2200, &s3c_qos->s3cqos3);
144 writel(0x00002032, &s3c_qos->s3cqos4);
145 writel(0x20960010, &s3c_qos->s3cqos5);
146 writel(0x20302030, &s3c_qos->s3cqos6);
147 writel(0x20AA2200, &s3c_qos->s3cqos7);
148 writel(0x00002032, &s3c_qos->s3cqos8);
149
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]150 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]151 if (IS_R8A7791_ES2())
152 writel(0x80928092, &s3c_qos->s3cqos0);
153 else
154 writel(0x00820082, &s3c_qos->s3cqos0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]155 writel(0x20960020, &s3c_qos->s3cqos1);
156 writel(0x20302030, &s3c_qos->s3cqos2);
157 writel(0x20AA20DC, &s3c_qos->s3cqos3);
158 writel(0x00002032, &s3c_qos->s3cqos4);
159 writel(0x20960020, &s3c_qos->s3cqos5);
160 writel(0x20302030, &s3c_qos->s3cqos6);
161 writel(0x20AA20DC, &s3c_qos->s3cqos7);
162 writel(0x00002032, &s3c_qos->s3cqos8);
163
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]164 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]165 writel(0x00820082, &s3c_qos->s3cqos0);
166 writel(0x20960020, &s3c_qos->s3cqos1);
167 writel(0x20302030, &s3c_qos->s3cqos2);
168 writel(0x20AA20FA, &s3c_qos->s3cqos3);
169 writel(0x00002032, &s3c_qos->s3cqos4);
170 writel(0x20960020, &s3c_qos->s3cqos5);
171 writel(0x20302030, &s3c_qos->s3cqos6);
172 writel(0x20AA20FA, &s3c_qos->s3cqos7);
173 writel(0x00002032, &s3c_qos->s3cqos8);
174
175 /* DBSC -QoS */
176 /* DBSC0 - Read */
177 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]178 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]179 writel(0x00000002, &qos_addr->dblgcnt);
180 writel(0x00002096, &qos_addr->dbtmval0);
181 writel(0x00002064, &qos_addr->dbtmval1);
182 writel(0x00002032, &qos_addr->dbtmval2);
183 writel(0x00001FB0, &qos_addr->dbtmval3);
184 writel(0x00000001, &qos_addr->dbrqctr);
185 writel(0x00002078, &qos_addr->dbthres0);
186 writel(0x0000204B, &qos_addr->dbthres1);
187 writel(0x00001FE7, &qos_addr->dbthres2);
188 writel(0x00000001, &qos_addr->dblgqon);
189 }
190
191 /* DBSC0 - Write */
192 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]193 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]194 writel(0x00000002, &qos_addr->dblgcnt);
195 writel(0x000020EB, &qos_addr->dbtmval0);
196 writel(0x0000206E, &qos_addr->dbtmval1);
197 writel(0x00002050, &qos_addr->dbtmval2);
198 writel(0x0000203A, &qos_addr->dbtmval3);
199 writel(0x00000001, &qos_addr->dbrqctr);
200 writel(0x00002078, &qos_addr->dbthres0);
201 writel(0x0000205A, &qos_addr->dbthres1);
202 writel(0x0000203C, &qos_addr->dbthres2);
203 writel(0x00000001, &qos_addr->dblgqon);
204 }
205
206 /* DBSC1 - Read */
207 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]208 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]209 writel(0x00000002, &qos_addr->dblgcnt);
210 writel(0x00002096, &qos_addr->dbtmval0);
211 writel(0x00002064, &qos_addr->dbtmval1);
212 writel(0x00002032, &qos_addr->dbtmval2);
213 writel(0x00001FB0, &qos_addr->dbtmval3);
214 writel(0x00000001, &qos_addr->dbrqctr);
215 writel(0x00002078, &qos_addr->dbthres0);
216 writel(0x0000204B, &qos_addr->dbthres1);
217 writel(0x00001FE7, &qos_addr->dbthres2);
218 writel(0x00000001, &qos_addr->dblgqon);
219 }
220
221 /* DBSC1 - Write */
222 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]223 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]224 writel(0x00000002, &qos_addr->dblgcnt);
225 writel(0x000020EB, &qos_addr->dbtmval0);
226 writel(0x0000206E, &qos_addr->dbtmval1);
227 writel(0x00002050, &qos_addr->dbtmval2);
228 writel(0x0000203A, &qos_addr->dbtmval3);
229 writel(0x00000001, &qos_addr->dbrqctr);
230 writel(0x00002078, &qos_addr->dbthres0);
231 writel(0x0000205A, &qos_addr->dbthres1);
232 writel(0x0000203C, &qos_addr->dbthres2);
233 writel(0x00000001, &qos_addr->dblgqon);
234 }
235
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]236 /* CCI-400 -QoS */
237 writel(0x20001000, CCI_400_MAXOT_1);
238 writel(0x20001000, CCI_400_MAXOT_2);
239 writel(0x0000000C, CCI_400_QOSCNTL_1);
240 writel(0x0000000C, CCI_400_QOSCNTL_2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]241
242 /* MXI -QoS */
243 /* Transaction Control (MXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]244 mxi = (struct rcar_mxi *)MXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]245 writel(0x00000013, &mxi->mxrtcr);
246 writel(0x00000013, &mxi->mxwtcr);
247 writel(0x00780080, &mxi->mxsaar0);
248 writel(0x02000800, &mxi->mxsaar1);
249
250 /* QoS Control (MXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]251 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]252 writel(0x0000000C, &mxi_qos->vspdu0);
253 writel(0x0000000C, &mxi_qos->vspdu1);
254 writel(0x0000000D, &mxi_qos->du0);
255 writel(0x0000000D, &mxi_qos->du1);
256
257 /* AXI -QoS */
258 /* Transaction Control (MXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]259 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]260 writel(0x00000002, &axi_qos->qosconf);
261 writel(0x00002245, &axi_qos->qosctset0);
262 writel(0x00002096, &axi_qos->qosctset1);
263 writel(0x00002030, &axi_qos->qosctset2);
264 writel(0x00002030, &axi_qos->qosctset3);
265 writel(0x00000001, &axi_qos->qosreqctr);
266 writel(0x00002064, &axi_qos->qosthres0);
267 writel(0x00002004, &axi_qos->qosthres1);
268 writel(0x00000000, &axi_qos->qosthres2);
269 writel(0x00000001, &axi_qos->qosqon);
270
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]271 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]272 writel(0x00000000, &axi_qos->qosconf);
273 writel(0x000020A6, &axi_qos->qosctset0);
274 writel(0x00000001, &axi_qos->qosreqctr);
275 writel(0x00002064, &axi_qos->qosthres0);
276 writel(0x00002004, &axi_qos->qosthres1);
277 writel(0x00000000, &axi_qos->qosthres2);
278 writel(0x00000001, &axi_qos->qosqon);
279
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]280 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]281 writel(0x00000000, &axi_qos->qosconf);
282 writel(0x000020A6, &axi_qos->qosctset0);
283 writel(0x00000001, &axi_qos->qosreqctr);
284 writel(0x00002064, &axi_qos->qosthres0);
285 writel(0x00002004, &axi_qos->qosthres1);
286 writel(0x00000000, &axi_qos->qosthres2);
287 writel(0x00000001, &axi_qos->qosqon);
288
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]289 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]290 writel(0x00000000, &axi_qos->qosconf);
291 writel(0x00002021, &axi_qos->qosctset0);
292 writel(0x00000001, &axi_qos->qosreqctr);
293 writel(0x00002064, &axi_qos->qosthres0);
294 writel(0x00002004, &axi_qos->qosthres1);
295 writel(0x00000000, &axi_qos->qosthres2);
296 writel(0x00000001, &axi_qos->qosqon);
297
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]298 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]299 writel(0x00000000, &axi_qos->qosconf);
300 writel(0x00002037, &axi_qos->qosctset0);
301 writel(0x00000001, &axi_qos->qosreqctr);
302 writel(0x00002064, &axi_qos->qosthres0);
303 writel(0x00002004, &axi_qos->qosthres1);
304 writel(0x00000000, &axi_qos->qosthres2);
305 writel(0x00000001, &axi_qos->qosqon);
306
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]307 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]308 writel(0x00000002, &axi_qos->qosconf);
309 writel(0x00002245, &axi_qos->qosctset0);
310 writel(0x00002096, &axi_qos->qosctset1);
311 writel(0x00002030, &axi_qos->qosctset2);
312 writel(0x00002030, &axi_qos->qosctset3);
313 writel(0x00000001, &axi_qos->qosreqctr);
314 writel(0x00002064, &axi_qos->qosthres0);
315 writel(0x00002004, &axi_qos->qosthres1);
316 writel(0x00000000, &axi_qos->qosthres2);
317 writel(0x00000001, &axi_qos->qosqon);
318
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]319 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]320 writel(0x00000002, &axi_qos->qosconf);
321 writel(0x00002245, &axi_qos->qosctset0);
322 writel(0x00002096, &axi_qos->qosctset1);
323 writel(0x00002030, &axi_qos->qosctset2);
324 writel(0x00002030, &axi_qos->qosctset3);
325 writel(0x00000001, &axi_qos->qosreqctr);
326 writel(0x00002064, &axi_qos->qosthres0);
327 writel(0x00002004, &axi_qos->qosthres1);
328 writel(0x00000000, &axi_qos->qosthres2);
329 writel(0x00000001, &axi_qos->qosqon);
330
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]331 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]332 writel(0x00000002, &axi_qos->qosconf);
333 writel(0x00002245, &axi_qos->qosctset0);
334 writel(0x00002096, &axi_qos->qosctset1);
335 writel(0x00002030, &axi_qos->qosctset2);
336 writel(0x00002030, &axi_qos->qosctset3);
337 writel(0x00000001, &axi_qos->qosreqctr);
338 writel(0x00002064, &axi_qos->qosthres0);
339 writel(0x00002004, &axi_qos->qosthres1);
340 writel(0x00000000, &axi_qos->qosthres2);
341 writel(0x00000001, &axi_qos->qosqon);
342
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]343 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]344 writel(0x00000000, &axi_qos->qosconf);
345 writel(0x0000214C, &axi_qos->qosctset0);
346 writel(0x00000001, &axi_qos->qosreqctr);
347 writel(0x00002064, &axi_qos->qosthres0);
348 writel(0x00002004, &axi_qos->qosthres1);
349 writel(0x00000000, &axi_qos->qosthres2);
350 writel(0x00000001, &axi_qos->qosqon);
351
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]352 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]353 writel(0x00000001, &axi_qos->qosconf);
354 writel(0x00002004, &axi_qos->qosctset0);
355 writel(0x00002096, &axi_qos->qosctset1);
356 writel(0x00002030, &axi_qos->qosctset2);
357 writel(0x00002030, &axi_qos->qosctset3);
358 writel(0x00000001, &axi_qos->qosreqctr);
359 writel(0x00002064, &axi_qos->qosthres0);
360 writel(0x00002004, &axi_qos->qosthres1);
361 writel(0x00000000, &axi_qos->qosthres2);
362 writel(0x00000001, &axi_qos->qosqon);
363
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]364 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]365 writel(0x00000001, &axi_qos->qosconf);
366 writel(0x00002004, &axi_qos->qosctset0);
367 writel(0x00002096, &axi_qos->qosctset1);
368 writel(0x00002030, &axi_qos->qosctset2);
369 writel(0x00002030, &axi_qos->qosctset3);
370 writel(0x00000001, &axi_qos->qosreqctr);
371 writel(0x00002064, &axi_qos->qosthres0);
372 writel(0x00002004, &axi_qos->qosthres1);
373 writel(0x00000000, &axi_qos->qosthres2);
374 writel(0x00000001, &axi_qos->qosqon);
375
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]376 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]377 writel(0x00000001, &axi_qos->qosconf);
378 writel(0x00002004, &axi_qos->qosctset0);
379 writel(0x00002096, &axi_qos->qosctset1);
380 writel(0x00002030, &axi_qos->qosctset2);
381 writel(0x00002030, &axi_qos->qosctset3);
382 writel(0x00000001, &axi_qos->qosreqctr);
383 writel(0x00002064, &axi_qos->qosthres0);
384 writel(0x00002004, &axi_qos->qosthres1);
385 writel(0x00000000, &axi_qos->qosthres2);
386 writel(0x00000001, &axi_qos->qosqon);
387
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]388 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]389 writel(0x00000001, &axi_qos->qosconf);
390 writel(0x00002004, &axi_qos->qosctset0);
391 writel(0x00002096, &axi_qos->qosctset1);
392 writel(0x00002030, &axi_qos->qosctset2);
393 writel(0x00002030, &axi_qos->qosctset3);
394 writel(0x00000001, &axi_qos->qosreqctr);
395 writel(0x00002064, &axi_qos->qosthres0);
396 writel(0x00002004, &axi_qos->qosthres1);
397 writel(0x00000000, &axi_qos->qosthres2);
398 writel(0x00000001, &axi_qos->qosqon);
399
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]400 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]401 writel(0x00000001, &axi_qos->qosconf);
402 writel(0x00002004, &axi_qos->qosctset0);
403 writel(0x00002096, &axi_qos->qosctset1);
404 writel(0x00002030, &axi_qos->qosctset2);
405 writel(0x00002030, &axi_qos->qosctset3);
406 writel(0x00000001, &axi_qos->qosreqctr);
407 writel(0x00002064, &axi_qos->qosthres0);
408 writel(0x00002004, &axi_qos->qosthres1);
409 writel(0x00000000, &axi_qos->qosthres2);
410 writel(0x00000001, &axi_qos->qosqon);
411
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]412 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]413 writel(0x00000000, &axi_qos->qosconf);
414 writel(0x00002021, &axi_qos->qosctset0);
415 writel(0x00000001, &axi_qos->qosreqctr);
416 writel(0x00002064, &axi_qos->qosthres0);
417 writel(0x00002004, &axi_qos->qosthres1);
418 writel(0x00000000, &axi_qos->qosthres2);
419 writel(0x00000001, &axi_qos->qosqon);
420
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]421 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]422 writel(0x00000000, &axi_qos->qosconf);
423 writel(0x00002021, &axi_qos->qosctset0);
424 writel(0x00000001, &axi_qos->qosreqctr);
425 writel(0x00002064, &axi_qos->qosthres0);
426 writel(0x00002004, &axi_qos->qosthres1);
427 writel(0x00000000, &axi_qos->qosthres2);
428 writel(0x00000001, &axi_qos->qosqon);
429
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]430 axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]431 writel(0x00000000, &axi_qos->qosconf);
432 writel(0x0000214C, &axi_qos->qosctset0);
433 writel(0x00000001, &axi_qos->qosreqctr);
434 writel(0x00002064, &axi_qos->qosthres0);
435 writel(0x00002004, &axi_qos->qosthres1);
436 writel(0x00000000, &axi_qos->qosthres2);
437 writel(0x00000001, &axi_qos->qosqon);
438
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]439 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]440 writel(0x00000002, &axi_qos->qosconf);
441 writel(0x00002245, &axi_qos->qosctset0);
442 writel(0x00002096, &axi_qos->qosctset1);
443 writel(0x00002030, &axi_qos->qosctset2);
444 writel(0x00002030, &axi_qos->qosctset3);
445 writel(0x00000001, &axi_qos->qosreqctr);
446 writel(0x00002064, &axi_qos->qosthres0);
447 writel(0x00002004, &axi_qos->qosthres1);
448 writel(0x00000000, &axi_qos->qosthres2);
449 writel(0x00000001, &axi_qos->qosqon);
450
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]451 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]452 writel(0x00000000, &axi_qos->qosconf);
453 writel(0x000020A6, &axi_qos->qosctset0);
454 writel(0x00000001, &axi_qos->qosreqctr);
455 writel(0x00002064, &axi_qos->qosthres0);
456 writel(0x00002004, &axi_qos->qosthres1);
457 writel(0x00000000, &axi_qos->qosthres2);
458 writel(0x00000001, &axi_qos->qosqon);
459
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]460 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]461 writel(0x00000000, &axi_qos->qosconf);
462 writel(0x000020A6, &axi_qos->qosctset0);
463 writel(0x00000001, &axi_qos->qosreqctr);
464 writel(0x00002064, &axi_qos->qosthres0);
465 writel(0x00002004, &axi_qos->qosthres1);
466 writel(0x00000000, &axi_qos->qosthres2);
467 writel(0x00000001, &axi_qos->qosqon);
468
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]469 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]470 writel(0x00000000, &axi_qos->qosconf);
471 writel(0x00002053, &axi_qos->qosctset0);
472 writel(0x00000001, &axi_qos->qosreqctr);
473 writel(0x00002064, &axi_qos->qosthres0);
474 writel(0x00002004, &axi_qos->qosthres1);
475 writel(0x00000000, &axi_qos->qosthres2);
476 writel(0x00000001, &axi_qos->qosqon);
477
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]478 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]479 writel(0x00000000, &axi_qos->qosconf);
480 writel(0x00002053, &axi_qos->qosctset0);
481 writel(0x00000001, &axi_qos->qosreqctr);
482 writel(0x00002064, &axi_qos->qosthres0);
483 writel(0x00002004, &axi_qos->qosthres1);
484 writel(0x00000000, &axi_qos->qosthres2);
485 writel(0x00000001, &axi_qos->qosqon);
486
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]487 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]488 writel(0x00000000, &axi_qos->qosconf);
489 writel(0x00002053, &axi_qos->qosctset0);
490 writel(0x00000001, &axi_qos->qosreqctr);
491 writel(0x00002064, &axi_qos->qosthres0);
492 writel(0x00002004, &axi_qos->qosthres1);
493 writel(0x00000000, &axi_qos->qosthres2);
494 writel(0x00000001, &axi_qos->qosqon);
495
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]496 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]497 writel(0x00000000, &axi_qos->qosconf);
498 writel(0x0000214C, &axi_qos->qosctset0);
499 writel(0x00000001, &axi_qos->qosreqctr);
500 writel(0x00002064, &axi_qos->qosthres0);
501 writel(0x00002004, &axi_qos->qosthres1);
502 writel(0x00000000, &axi_qos->qosthres2);
503 writel(0x00000001, &axi_qos->qosqon);
504
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]505 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]506 writel(0x00000002, &axi_qos->qosconf);
507 writel(0x00002245, &axi_qos->qosctset0);
508 writel(0x00000001, &axi_qos->qosreqctr);
509 writel(0x00002064, &axi_qos->qosthres0);
510 writel(0x00002004, &axi_qos->qosthres1);
511 writel(0x00000000, &axi_qos->qosthres2);
512 writel(0x00000001, &axi_qos->qosqon);
513
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]514 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]515 writel(0x00000000, &axi_qos->qosconf);
516 writel(0x00002029, &axi_qos->qosctset0);
517 writel(0x00000001, &axi_qos->qosreqctr);
518 writel(0x00002064, &axi_qos->qosthres0);
519 writel(0x00002004, &axi_qos->qosthres1);
520 writel(0x00000000, &axi_qos->qosthres2);
521 writel(0x00000001, &axi_qos->qosqon);
522
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]523 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]524 writel(0x00000002, &axi_qos->qosconf);
525 writel(0x00002245, &axi_qos->qosctset0);
526 writel(0x00000001, &axi_qos->qosreqctr);
527 writel(0x00002064, &axi_qos->qosthres0);
528 writel(0x00002004, &axi_qos->qosthres1);
529 writel(0x00000000, &axi_qos->qosthres2);
530 writel(0x00000001, &axi_qos->qosqon);
531
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]532 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]533 writel(0x00000000, &axi_qos->qosconf);
534 writel(0x00002053, &axi_qos->qosctset0);
535 writel(0x00000001, &axi_qos->qosreqctr);
536 writel(0x00002064, &axi_qos->qosthres0);
537 writel(0x00002004, &axi_qos->qosthres1);
538 writel(0x00000000, &axi_qos->qosthres2);
539 writel(0x00000001, &axi_qos->qosqon);
540
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]541 axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]542 writel(0x00000000, &axi_qos->qosconf);
543 writel(0x000020A6, &axi_qos->qosctset0);
544 writel(0x00000001, &axi_qos->qosreqctr);
545 writel(0x00002064, &axi_qos->qosthres0);
546 writel(0x00002004, &axi_qos->qosthres1);
547 writel(0x00000000, &axi_qos->qosthres2);
548 writel(0x00000001, &axi_qos->qosqon);
549
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]550 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]551 writel(0x00000000, &axi_qos->qosconf);
552 writel(0x00002053, &axi_qos->qosctset0);
553 writel(0x00000001, &axi_qos->qosreqctr);
554 writel(0x00002064, &axi_qos->qosthres0);
555 writel(0x00002004, &axi_qos->qosthres1);
556 writel(0x00000000, &axi_qos->qosthres2);
557 writel(0x00000001, &axi_qos->qosqon);
558
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]559 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]560 writel(0x00000002, &axi_qos->qosconf);
561 writel(0x00002245, &axi_qos->qosctset0);
562 writel(0x00000001, &axi_qos->qosreqctr);
563 writel(0x00002064, &axi_qos->qosthres0);
564 writel(0x00002004, &axi_qos->qosthres1);
565 writel(0x00000000, &axi_qos->qosthres2);
566 writel(0x00000001, &axi_qos->qosqon);
567
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]568 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]569 writel(0x00000000, &axi_qos->qosconf);
570 writel(0x00002053, &axi_qos->qosctset0);
571 writel(0x00000001, &axi_qos->qosreqctr);
572 writel(0x00002064, &axi_qos->qosthres0);
573 writel(0x00002004, &axi_qos->qosthres1);
574 writel(0x00000000, &axi_qos->qosthres2);
575 writel(0x00000001, &axi_qos->qosqon);
576
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]577 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]578 writel(0x00000000, &axi_qos->qosconf);
579 writel(0x00002053, &axi_qos->qosctset0);
580 writel(0x00000001, &axi_qos->qosreqctr);
581 writel(0x00002064, &axi_qos->qosthres0);
582 writel(0x00002004, &axi_qos->qosthres1);
583 writel(0x00000000, &axi_qos->qosthres2);
584 writel(0x00000001, &axi_qos->qosqon);
585
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]586 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]587 writel(0x00000000, &axi_qos->qosconf);
588 writel(0x0000214C, &axi_qos->qosctset0);
589 writel(0x00000001, &axi_qos->qosreqctr);
590 writel(0x00002064, &axi_qos->qosthres0);
591 writel(0x00002004, &axi_qos->qosthres1);
592 writel(0x00000000, &axi_qos->qosthres2);
593 writel(0x00000001, &axi_qos->qosqon);
594
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]595 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]596 writel(0x00000000, &axi_qos->qosconf);
597 writel(0x0000214C, &axi_qos->qosctset0);
598 writel(0x00000001, &axi_qos->qosreqctr);
599 writel(0x00002064, &axi_qos->qosthres0);
600 writel(0x00002004, &axi_qos->qosthres1);
601 writel(0x00000000, &axi_qos->qosthres2);
602 writel(0x00000001, &axi_qos->qosqon);
603
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]604 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]605 writel(0x00000000, &axi_qos->qosconf);
606 writel(0x000020A6, &axi_qos->qosctset0);
607 writel(0x00000001, &axi_qos->qosreqctr);
608 writel(0x00002064, &axi_qos->qosthres0);
609 writel(0x00002004, &axi_qos->qosthres1);
610 writel(0x00000000, &axi_qos->qosthres2);
611 writel(0x00000001, &axi_qos->qosqon);
612
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]613 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]614 writel(0x00000000, &axi_qos->qosconf);
615 writel(0x00002053, &axi_qos->qosctset0);
616 writel(0x00000001, &axi_qos->qosreqctr);
617 writel(0x00002064, &axi_qos->qosthres0);
618 writel(0x00002004, &axi_qos->qosthres1);
619 writel(0x00000000, &axi_qos->qosthres2);
620 writel(0x00000001, &axi_qos->qosqon);
621
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]622 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]623 writel(0x00000000, &axi_qos->qosconf);
624 writel(0x00002053, &axi_qos->qosctset0);
625 writel(0x00000001, &axi_qos->qosreqctr);
626 writel(0x00002064, &axi_qos->qosthres0);
627 writel(0x00002004, &axi_qos->qosthres1);
628 writel(0x00000000, &axi_qos->qosthres2);
629 writel(0x00000001, &axi_qos->qosqon);
630
631 /* QoS Register (RT-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]632 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]633 writel(0x00000000, &axi_qos->qosconf);
634 writel(0x00002053, &axi_qos->qosctset0);
635 writel(0x00002096, &axi_qos->qosctset1);
636 writel(0x00002030, &axi_qos->qosctset2);
637 writel(0x00002030, &axi_qos->qosctset3);
638 writel(0x00000001, &axi_qos->qosreqctr);
639 writel(0x00002064, &axi_qos->qosthres0);
640 writel(0x00002004, &axi_qos->qosthres1);
641 writel(0x00000000, &axi_qos->qosthres2);
642 writel(0x00000001, &axi_qos->qosqon);
643
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]644 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]645 writel(0x00000000, &axi_qos->qosconf);
646 writel(0x00002053, &axi_qos->qosctset0);
647 writel(0x00002096, &axi_qos->qosctset1);
648 writel(0x00002030, &axi_qos->qosctset2);
649 writel(0x00002030, &axi_qos->qosctset3);
650 writel(0x00000001, &axi_qos->qosreqctr);
651 writel(0x00002064, &axi_qos->qosthres0);
652 writel(0x00002004, &axi_qos->qosthres1);
653 writel(0x00000000, &axi_qos->qosthres2);
654 writel(0x00000001, &axi_qos->qosqon);
655
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]656 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]657 writel(0x00000000, &axi_qos->qosconf);
658 writel(0x00002299, &axi_qos->qosctset0);
659 writel(0x00000001, &axi_qos->qosreqctr);
660 writel(0x00002064, &axi_qos->qosthres0);
661 writel(0x00002004, &axi_qos->qosthres1);
662 writel(0x00000000, &axi_qos->qosthres2);
663 writel(0x00000001, &axi_qos->qosqon);
664
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]665 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]666 writel(0x00000000, &axi_qos->qosconf);
667 writel(0x00002029, &axi_qos->qosctset0);
668 writel(0x00000001, &axi_qos->qosreqctr);
669 writel(0x00002064, &axi_qos->qosthres0);
670 writel(0x00002004, &axi_qos->qosthres1);
671 writel(0x00000000, &axi_qos->qosthres2);
672 writel(0x00000001, &axi_qos->qosqon);
673
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]674 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]675 writel(0x00000002, &axi_qos->qosconf);
676 writel(0x00002245, &axi_qos->qosctset0);
677 writel(0x00002096, &axi_qos->qosctset1);
678 writel(0x00002030, &axi_qos->qosctset2);
679 writel(0x00002030, &axi_qos->qosctset3);
680 writel(0x00000001, &axi_qos->qosreqctr);
681 writel(0x00002064, &axi_qos->qosthres0);
682 writel(0x00002004, &axi_qos->qosthres1);
683 writel(0x00000000, &axi_qos->qosthres2);
684 writel(0x00000001, &axi_qos->qosqon);
685
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]686 axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]687 writel(0x00000000, &axi_qos->qosconf);
688 writel(0x00002029, &axi_qos->qosctset0);
689 writel(0x00002096, &axi_qos->qosctset1);
690 writel(0x00002030, &axi_qos->qosctset2);
691 writel(0x00002030, &axi_qos->qosctset3);
692 writel(0x00000001, &axi_qos->qosreqctr);
693 writel(0x00002064, &axi_qos->qosthres0);
694 writel(0x00002004, &axi_qos->qosthres1);
695 writel(0x00000000, &axi_qos->qosthres2);
696 writel(0x00000001, &axi_qos->qosqon);
697
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]698 axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]699 writel(0x00000002, &axi_qos->qosconf);
700 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]701 writel(0x00000001, &axi_qos->qosreqctr);
702 writel(0x00002064, &axi_qos->qosthres0);
703 writel(0x00002004, &axi_qos->qosthres1);
704 writel(0x00000000, &axi_qos->qosthres2);
705 writel(0x00000001, &axi_qos->qosqon);
706
707 /* QoS Register (MP-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]708 axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]709 writel(0x00000000, &axi_qos->qosconf);
710 writel(0x00002037, &axi_qos->qosctset0);
711 writel(0x00000001, &axi_qos->qosreqctr);
712 writel(0x00002064, &axi_qos->qosthres0);
713 writel(0x00002004, &axi_qos->qosthres1);
714 writel(0x00000000, &axi_qos->qosthres2);
715 writel(0x00000001, &axi_qos->qosqon);
716
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]717 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]718 writel(0x00000001, &axi_qos->qosconf);
719 writel(0x00002014, &axi_qos->qosctset0);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]720 writel(0x00000040, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]721 writel(0x00002064, &axi_qos->qosthres0);
722 writel(0x00002004, &axi_qos->qosthres1);
723 writel(0x00000000, &axi_qos->qosthres2);
724 writel(0x00000001, &axi_qos->qosqon);
725
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]726 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]727 writel(0x00000001, &axi_qos->qosconf);
728 writel(0x00002014, &axi_qos->qosctset0);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]729 writel(0x00000040, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]730 writel(0x00002064, &axi_qos->qosthres0);
731 writel(0x00002004, &axi_qos->qosthres1);
732 writel(0x00000000, &axi_qos->qosthres2);
733 writel(0x00000001, &axi_qos->qosqon);
734
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]735 axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]736 writel(0x00000001, &axi_qos->qosconf);
737 writel(0x00001FF0, &axi_qos->qosctset0);
738 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]739 writel(0x00002064, &axi_qos->qosthres0);
740 writel(0x00002004, &axi_qos->qosthres1);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]741 writel(0x00002001, &axi_qos->qosthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]742 writel(0x00000001, &axi_qos->qosqon);
743
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]744 axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]745 writel(0x00000001, &axi_qos->qosconf);
746 writel(0x00002004, &axi_qos->qosctset0);
747 writel(0x00002096, &axi_qos->qosctset1);
748 writel(0x00002030, &axi_qos->qosctset2);
749 writel(0x00002030, &axi_qos->qosctset3);
750 writel(0x00000001, &axi_qos->qosreqctr);
751 writel(0x00002064, &axi_qos->qosthres0);
752 writel(0x00002004, &axi_qos->qosthres1);
753 writel(0x00000000, &axi_qos->qosthres2);
754 writel(0x00000001, &axi_qos->qosqon);
755
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]756 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]757 writel(0x00000000, &axi_qos->qosconf);
758 writel(0x00002053, &axi_qos->qosctset0);
759 writel(0x00000001, &axi_qos->qosreqctr);
760 writel(0x00002064, &axi_qos->qosthres0);
761 writel(0x00002004, &axi_qos->qosthres1);
762 writel(0x00000000, &axi_qos->qosthres2);
763 writel(0x00000001, &axi_qos->qosqon);
764
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]765 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]766 writel(0x00000000, &axi_qos->qosconf);
767 writel(0x0000206E, &axi_qos->qosctset0);
768 writel(0x00000001, &axi_qos->qosreqctr);
769 writel(0x00002064, &axi_qos->qosthres0);
770 writel(0x00002004, &axi_qos->qosthres1);
771 writel(0x00000000, &axi_qos->qosthres2);
772 writel(0x00000001, &axi_qos->qosqon);
773
774 /* QoS Register (SYS-AXI256) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]775 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]776 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]777 if (IS_R8A7791_ES2())
778 writel(0x000020EB, &axi_qos->qosctset0);
779 else
780 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]781 writel(0x00002096, &axi_qos->qosctset1);
782 writel(0x00002030, &axi_qos->qosctset2);
783 writel(0x00002030, &axi_qos->qosctset3);
784 writel(0x00000001, &axi_qos->qosreqctr);
785 writel(0x00002064, &axi_qos->qosthres0);
786 writel(0x00002004, &axi_qos->qosthres1);
787 writel(0x00000000, &axi_qos->qosthres2);
788 writel(0x00000001, &axi_qos->qosqon);
789
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]790 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]791 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]792 if (IS_R8A7791_ES2())
793 writel(0x000020EB, &axi_qos->qosctset0);
794 else
795 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]796 writel(0x00002096, &axi_qos->qosctset1);
797 writel(0x00002030, &axi_qos->qosctset2);
798 writel(0x00002030, &axi_qos->qosctset3);
799 writel(0x00000001, &axi_qos->qosreqctr);
800 writel(0x00002064, &axi_qos->qosthres0);
801 writel(0x00002004, &axi_qos->qosthres1);
802 writel(0x00000000, &axi_qos->qosthres2);
803 writel(0x00000001, &axi_qos->qosqon);
804
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]805 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]806 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]807 if (IS_R8A7791_ES2())
808 writel(0x000020EB, &axi_qos->qosctset0);
809 else
810 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]811 writel(0x00002096, &axi_qos->qosctset1);
812 writel(0x00002030, &axi_qos->qosctset2);
813 writel(0x00002030, &axi_qos->qosctset3);
814 writel(0x00000001, &axi_qos->qosreqctr);
815 writel(0x00002064, &axi_qos->qosthres0);
816 writel(0x00002004, &axi_qos->qosthres1);
817 writel(0x00000000, &axi_qos->qosthres2);
818 writel(0x00000001, &axi_qos->qosqon);
819
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]820 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]821 writel(0x00000002, &axi_qos->qosconf);
822 writel(0x00002245, &axi_qos->qosctset0);
823 writel(0x00002096, &axi_qos->qosctset1);
824 writel(0x00002030, &axi_qos->qosctset2);
825 writel(0x00002030, &axi_qos->qosctset3);
826 writel(0x00000001, &axi_qos->qosreqctr);
827 writel(0x00002064, &axi_qos->qosthres0);
828 writel(0x00002004, &axi_qos->qosthres1);
829 writel(0x00000000, &axi_qos->qosthres2);
830 writel(0x00000001, &axi_qos->qosqon);
831
832 /* QoS Register (CCI-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]833 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]834 writel(0x00000001, &axi_qos->qosconf);
835 writel(0x00002004, &axi_qos->qosctset0);
836 writel(0x00002096, &axi_qos->qosctset1);
837 writel(0x00002030, &axi_qos->qosctset2);
838 writel(0x00002030, &axi_qos->qosctset3);
839 writel(0x00000001, &axi_qos->qosreqctr);
840 writel(0x00002064, &axi_qos->qosthres0);
841 writel(0x00002004, &axi_qos->qosthres1);
842 writel(0x00000000, &axi_qos->qosthres2);
843 writel(0x00000001, &axi_qos->qosqon);
844
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]845 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]846 writel(0x00000002, &axi_qos->qosconf);
847 writel(0x00002245, &axi_qos->qosctset0);
848 writel(0x00002096, &axi_qos->qosctset1);
849 writel(0x00002030, &axi_qos->qosctset2);
850 writel(0x00002030, &axi_qos->qosctset3);
851 writel(0x00000001, &axi_qos->qosreqctr);
852 writel(0x00002064, &axi_qos->qosthres0);
853 writel(0x00002004, &axi_qos->qosthres1);
854 writel(0x00000000, &axi_qos->qosthres2);
855 writel(0x00000001, &axi_qos->qosqon);
856
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]857 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]858 writel(0x00000001, &axi_qos->qosconf);
859 writel(0x00002004, &axi_qos->qosctset0);
860 writel(0x00002096, &axi_qos->qosctset1);
861 writel(0x00002030, &axi_qos->qosctset2);
862 writel(0x00002030, &axi_qos->qosctset3);
863 writel(0x00000001, &axi_qos->qosreqctr);
864 writel(0x00002064, &axi_qos->qosthres0);
865 writel(0x00002004, &axi_qos->qosthres1);
866 writel(0x00000000, &axi_qos->qosthres2);
867 writel(0x00000001, &axi_qos->qosqon);
868
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]869 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]870 writel(0x00000001, &axi_qos->qosconf);
871 writel(0x00002004, &axi_qos->qosctset0);
872 writel(0x00002096, &axi_qos->qosctset1);
873 writel(0x00002030, &axi_qos->qosctset2);
874 writel(0x00002030, &axi_qos->qosctset3);
875 writel(0x00000001, &axi_qos->qosreqctr);
876 writel(0x00002064, &axi_qos->qosthres0);
877 writel(0x00002004, &axi_qos->qosthres1);
878 writel(0x00000000, &axi_qos->qosthres2);
879 writel(0x00000001, &axi_qos->qosqon);
880
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]881 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]882 writel(0x00000001, &axi_qos->qosconf);
883 writel(0x00002004, &axi_qos->qosctset0);
884 writel(0x00002096, &axi_qos->qosctset1);
885 writel(0x00002030, &axi_qos->qosctset2);
886 writel(0x00002030, &axi_qos->qosctset3);
887 writel(0x00000001, &axi_qos->qosreqctr);
888 writel(0x00002064, &axi_qos->qosthres0);
889 writel(0x00002004, &axi_qos->qosthres1);
890 writel(0x00000000, &axi_qos->qosthres2);
891 writel(0x00000001, &axi_qos->qosqon);
892
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]893 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]894 writel(0x00000002, &axi_qos->qosconf);
895 writel(0x00002245, &axi_qos->qosctset0);
896 writel(0x00002096, &axi_qos->qosctset1);
897 writel(0x00002030, &axi_qos->qosctset2);
898 writel(0x00002030, &axi_qos->qosctset3);
899 writel(0x00000001, &axi_qos->qosreqctr);
900 writel(0x00002064, &axi_qos->qosthres0);
901 writel(0x00002004, &axi_qos->qosthres1);
902 writel(0x00000000, &axi_qos->qosthres2);
903 writel(0x00000001, &axi_qos->qosqon);
904
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]905 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]906 writel(0x00000001, &axi_qos->qosconf);
907 writel(0x00002004, &axi_qos->qosctset0);
908 writel(0x00002096, &axi_qos->qosctset1);
909 writel(0x00002030, &axi_qos->qosctset2);
910 writel(0x00002030, &axi_qos->qosctset3);
911 writel(0x00000001, &axi_qos->qosreqctr);
912 writel(0x00002064, &axi_qos->qosthres0);
913 writel(0x00002004, &axi_qos->qosthres1);
914 writel(0x00000000, &axi_qos->qosthres2);
915 writel(0x00000001, &axi_qos->qosqon);
916
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]917 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]918 writel(0x00000001, &axi_qos->qosconf);
919 writel(0x00002004, &axi_qos->qosctset0);
920 writel(0x00002096, &axi_qos->qosctset1);
921 writel(0x00002030, &axi_qos->qosctset2);
922 writel(0x00002030, &axi_qos->qosctset3);
923 writel(0x00000001, &axi_qos->qosreqctr);
924 writel(0x00002064, &axi_qos->qosthres0);
925 writel(0x00002004, &axi_qos->qosthres1);
926 writel(0x00000000, &axi_qos->qosthres2);
927 writel(0x00000001, &axi_qos->qosqon);
928
929 /* QoS Register (Media-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]930 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]931 writel(0x00000002, &axi_qos->qosconf);
932 writel(0x000020DC, &axi_qos->qosctset0);
933 writel(0x00002096, &axi_qos->qosctset1);
934 writel(0x00002030, &axi_qos->qosctset2);
935 writel(0x00002030, &axi_qos->qosctset3);
936 writel(0x00000020, &axi_qos->qosreqctr);
937 writel(0x000020AA, &axi_qos->qosthres0);
938 writel(0x00002032, &axi_qos->qosthres1);
939 writel(0x00000001, &axi_qos->qosthres2);
940
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]941 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]942 writel(0x00000002, &axi_qos->qosconf);
943 writel(0x000020DC, &axi_qos->qosctset0);
944 writel(0x00002096, &axi_qos->qosctset1);
945 writel(0x00002030, &axi_qos->qosctset2);
946 writel(0x00002030, &axi_qos->qosctset3);
947 writel(0x00000020, &axi_qos->qosreqctr);
948 writel(0x000020AA, &axi_qos->qosthres0);
949 writel(0x00002032, &axi_qos->qosthres1);
950 writel(0x00000001, &axi_qos->qosthres2);
951
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]952 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]953 writel(0x00000001, &axi_qos->qosconf);
954 writel(0x00002190, &axi_qos->qosctset0);
955 writel(0x00000020, &axi_qos->qosreqctr);
956 writel(0x00002064, &axi_qos->qosthres0);
957 writel(0x00002004, &axi_qos->qosthres1);
958 writel(0x00000001, &axi_qos->qosthres2);
959 writel(0x00000001, &axi_qos->qosqon);
960
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]961 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]962 writel(0x00000001, &axi_qos->qosconf);
963 writel(0x00002190, &axi_qos->qosctset0);
964 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]965 if (IS_R8A7791_ES2()) {
966 writel(0x00000001, &axi_qos->qosthres0);
967 writel(0x00000001, &axi_qos->qosthres1);
968 } else {
969 writel(0x00002064, &axi_qos->qosthres0);
970 writel(0x00002004, &axi_qos->qosthres1);
971 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]972 writel(0x00000001, &axi_qos->qosthres2);
973 writel(0x00000001, &axi_qos->qosqon);
974
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]975 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]976 writel(0x00000001, &axi_qos->qosconf);
977 writel(0x00002190, &axi_qos->qosctset0);
978 writel(0x00000020, &axi_qos->qosreqctr);
979 writel(0x00002064, &axi_qos->qosthres0);
980 writel(0x00002004, &axi_qos->qosthres1);
981 writel(0x00000001, &axi_qos->qosthres2);
982 writel(0x00000001, &axi_qos->qosqon);
983
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]984 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]985 writel(0x00000001, &axi_qos->qosconf);
986 writel(0x00002190, &axi_qos->qosctset0);
987 writel(0x00000020, &axi_qos->qosreqctr);
988 writel(0x00002064, &axi_qos->qosthres0);
989 writel(0x00002004, &axi_qos->qosthres1);
990 writel(0x00000001, &axi_qos->qosthres2);
991 writel(0x00000001, &axi_qos->qosqon);
992
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]993 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]994 writel(0x00000001, &axi_qos->qosconf);
995 writel(0x00002190, &axi_qos->qosctset0);
996 writel(0x00000020, &axi_qos->qosreqctr);
997 writel(0x00002064, &axi_qos->qosthres0);
998 writel(0x00002004, &axi_qos->qosthres1);
999 writel(0x00000001, &axi_qos->qosthres2);
1000 writel(0x00000001, &axi_qos->qosqon);
1001
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1002 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1003 writel(0x00000001, &axi_qos->qosconf);
1004 writel(0x00002190, &axi_qos->qosctset0);
1005 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1006 if (IS_R8A7791_ES2()) {
1007 writel(0x00000001, &axi_qos->qosthres0);
1008 writel(0x00000001, &axi_qos->qosthres1);
1009 } else {
1010 writel(0x00002064, &axi_qos->qosthres0);
1011 writel(0x00002004, &axi_qos->qosthres1);
1012 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1013 writel(0x00000001, &axi_qos->qosthres2);
1014 writel(0x00000001, &axi_qos->qosqon);
1015
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1016 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1017 writel(0x00000001, &axi_qos->qosconf);
1018 writel(0x00002190, &axi_qos->qosctset0);
1019 writel(0x00000020, &axi_qos->qosreqctr);
1020 writel(0x00002064, &axi_qos->qosthres0);
1021 writel(0x00002004, &axi_qos->qosthres1);
1022 writel(0x00000001, &axi_qos->qosthres2);
1023 writel(0x00000001, &axi_qos->qosqon);
1024
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1025 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1026 writel(0x00000001, &axi_qos->qosconf);
1027 writel(0x00002190, &axi_qos->qosctset0);
1028 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1029 if (IS_R8A7791_ES2()) {
1030 writel(0x00000001, &axi_qos->qosthres0);
1031 writel(0x00000001, &axi_qos->qosthres1);
1032 } else {
1033 writel(0x00002064, &axi_qos->qosthres0);
1034 writel(0x00002004, &axi_qos->qosthres1);
1035 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1036 writel(0x00000001, &axi_qos->qosthres2);
1037 writel(0x00000001, &axi_qos->qosqon);
1038
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1039 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1040 writel(0x00000001, &axi_qos->qosconf);
1041 writel(0x00002190, &axi_qos->qosctset0);
1042 writel(0x00000020, &axi_qos->qosreqctr);
1043 writel(0x00002064, &axi_qos->qosthres0);
1044 writel(0x00002004, &axi_qos->qosthres1);
1045 writel(0x00000001, &axi_qos->qosthres2);
1046 writel(0x00000001, &axi_qos->qosqon);
1047
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1048 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1049 writel(0x00000001, &axi_qos->qosconf);
1050 writel(0x00002190, &axi_qos->qosctset0);
1051 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1052 if (IS_R8A7791_ES2()) {
1053 writel(0x00000001, &axi_qos->qosthres0);
1054 writel(0x00000001, &axi_qos->qosthres1);
1055 } else {
1056 writel(0x00002064, &axi_qos->qosthres0);
1057 writel(0x00002004, &axi_qos->qosthres1);
1058 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1059 writel(0x00000001, &axi_qos->qosthres2);
1060 writel(0x00000001, &axi_qos->qosqon);
1061
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1062 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1063 writel(0x00000001, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1064 if (IS_R8A7791_ES2())
1065 writel(0x00001FF0, &axi_qos->qosctset0);
1066 else
1067 writel(0x000020C8, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1068 writel(0x00000020, &axi_qos->qosreqctr);
1069 writel(0x00002064, &axi_qos->qosthres0);
1070 writel(0x00002004, &axi_qos->qosthres1);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1071 if (IS_R8A7791_ES2())
1072 writel(0x00002001, &axi_qos->qosthres2);
1073 else
1074 writel(0x00000001, &axi_qos->qosthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1075 writel(0x00000001, &axi_qos->qosqon);
1076
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1077 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1078 writel(0x00000001, &axi_qos->qosconf);
1079 writel(0x000020C8, &axi_qos->qosctset0);
1080 writel(0x00000020, &axi_qos->qosreqctr);
1081 writel(0x00002064, &axi_qos->qosthres0);
1082 writel(0x00002004, &axi_qos->qosthres1);
1083 writel(0x00000001, &axi_qos->qosthres2);
1084 writel(0x00000001, &axi_qos->qosqon);
1085
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1086 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1087 writel(0x00000001, &axi_qos->qosconf);
1088 writel(0x000020C8, &axi_qos->qosctset0);
1089 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1090 if (IS_R8A7791_ES2()) {
1091 writel(0x00000001, &axi_qos->qosthres0);
1092 writel(0x00000001, &axi_qos->qosthres1);
1093 } else {
1094 writel(0x00002064, &axi_qos->qosthres0);
1095 writel(0x00002004, &axi_qos->qosthres1);
1096 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1097 writel(0x00000001, &axi_qos->qosthres2);
1098 writel(0x00000001, &axi_qos->qosqon);
1099
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1100 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1101 writel(0x00000001, &axi_qos->qosconf);
1102 writel(0x000020C8, &axi_qos->qosctset0);
1103 writel(0x00000020, &axi_qos->qosreqctr);
1104 writel(0x00002064, &axi_qos->qosthres0);
1105 writel(0x00002004, &axi_qos->qosthres1);
1106 writel(0x00000001, &axi_qos->qosthres2);
1107 writel(0x00000001, &axi_qos->qosqon);
1108
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1109 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1110 writel(0x00000001, &axi_qos->qosconf);
1111 writel(0x000020C8, &axi_qos->qosctset0);
1112 writel(0x00000020, &axi_qos->qosreqctr);
1113 writel(0x00002064, &axi_qos->qosthres0);
1114 writel(0x00002004, &axi_qos->qosthres1);
1115 writel(0x00000001, &axi_qos->qosthres2);
1116 writel(0x00000001, &axi_qos->qosqon);
1117
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1118 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1119 writel(0x00000001, &axi_qos->qosconf);
1120 writel(0x000020C8, &axi_qos->qosctset0);
1121 writel(0x00000020, &axi_qos->qosreqctr);
1122 writel(0x00002064, &axi_qos->qosthres0);
1123 writel(0x00002004, &axi_qos->qosthres1);
1124 writel(0x00000001, &axi_qos->qosthres2);
1125 writel(0x00000001, &axi_qos->qosqon);
1126
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1127 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1128 writel(0x00000001, &axi_qos->qosconf);
1129 writel(0x000020C8, &axi_qos->qosctset0);
1130 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1131 if (IS_R8A7791_ES2()) {
1132 writel(0x00000001, &axi_qos->qosthres0);
1133 writel(0x00000001, &axi_qos->qosthres1);
1134 } else {
1135 writel(0x00002064, &axi_qos->qosthres0);
1136 writel(0x00002004, &axi_qos->qosthres1);
1137 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1138 writel(0x00000001, &axi_qos->qosthres2);
1139 writel(0x00000001, &axi_qos->qosqon);
1140
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1141 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1142 writel(0x00000001, &axi_qos->qosconf);
1143 writel(0x000020C8, &axi_qos->qosctset0);
1144 writel(0x00000020, &axi_qos->qosreqctr);
1145 writel(0x00002064, &axi_qos->qosthres0);
1146 writel(0x00002004, &axi_qos->qosthres1);
1147 writel(0x00000001, &axi_qos->qosthres2);
1148 writel(0x00000001, &axi_qos->qosqon);
1149
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1150 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1151 writel(0x00000001, &axi_qos->qosconf);
1152 writel(0x000020C8, &axi_qos->qosctset0);
1153 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1154 if (IS_R8A7791_ES2()) {
1155 writel(0x00000001, &axi_qos->qosthres0);
1156 writel(0x00000001, &axi_qos->qosthres1);
1157 } else {
1158 writel(0x00002064, &axi_qos->qosthres0);
1159 writel(0x00002004, &axi_qos->qosthres1);
1160 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1161 writel(0x00000001, &axi_qos->qosthres2);
1162 writel(0x00000001, &axi_qos->qosqon);
1163
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1164 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1165 writel(0x00000001, &axi_qos->qosconf);
1166 writel(0x000020C8, &axi_qos->qosctset0);
1167 writel(0x00000020, &axi_qos->qosreqctr);
1168 writel(0x00002064, &axi_qos->qosthres0);
1169 writel(0x00002004, &axi_qos->qosthres1);
1170 writel(0x00000001, &axi_qos->qosthres2);
1171 writel(0x00000001, &axi_qos->qosqon);
1172
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1173 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1174 writel(0x00000001, &axi_qos->qosconf);
1175 writel(0x000020C8, &axi_qos->qosctset0);
1176 writel(0x00000020, &axi_qos->qosreqctr);
1177 writel(0x00002064, &axi_qos->qosthres0);
1178 writel(0x00002004, &axi_qos->qosthres1);
1179 writel(0x00000001, &axi_qos->qosthres2);
1180 writel(0x00000001, &axi_qos->qosqon);
1181
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1182 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1183 if (IS_R8A7791_ES2())
1184 writel(0x00000003, &axi_qos->qosconf);
1185 else
1186 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1187 writel(0x000020C8, &axi_qos->qosctset0);
1188 writel(0x00002064, &axi_qos->qosthres0);
1189 writel(0x00002004, &axi_qos->qosthres1);
1190 writel(0x00000001, &axi_qos->qosthres2);
1191 writel(0x00000001, &axi_qos->qosqon);
1192
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1193 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1194 if (IS_R8A7791_ES2())
1195 writel(0x00000003, &axi_qos->qosconf);
1196 else
1197 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1198 writel(0x000020C8, &axi_qos->qosctset0);
1199 writel(0x00002064, &axi_qos->qosthres0);
1200 writel(0x00002004, &axi_qos->qosthres1);
1201 writel(0x00000001, &axi_qos->qosthres2);
1202 writel(0x00000001, &axi_qos->qosqon);
1203
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1204 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1205 if (IS_R8A7791_ES2())
1206 writel(0x00000003, &axi_qos->qosconf);
1207 else
1208 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1209 writel(0x000020C8, &axi_qos->qosctset0);
1210 writel(0x00002064, &axi_qos->qosthres0);
1211 writel(0x00002004, &axi_qos->qosthres1);
1212 writel(0x00000001, &axi_qos->qosthres2);
1213 writel(0x00000001, &axi_qos->qosqon);
1214
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1215 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1216 if (IS_R8A7791_ES2())
1217 writel(0x00000003, &axi_qos->qosconf);
1218 else
1219 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1220 writel(0x000020C8, &axi_qos->qosctset0);
1221 writel(0x00002064, &axi_qos->qosthres0);
1222 writel(0x00002004, &axi_qos->qosthres1);
1223 writel(0x00000001, &axi_qos->qosthres2);
1224 writel(0x00000001, &axi_qos->qosqon);
1225
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1226 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1227 if (IS_R8A7791_ES2())
1228 writel(0x00000003, &axi_qos->qosconf);
1229 else
1230 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1231 writel(0x00002063, &axi_qos->qosctset0);
1232 writel(0x00000001, &axi_qos->qosreqctr);
1233 writel(0x00002064, &axi_qos->qosthres0);
1234 writel(0x00002004, &axi_qos->qosthres1);
1235 writel(0x00000001, &axi_qos->qosthres2);
1236 writel(0x00000001, &axi_qos->qosqon);
1237
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1238 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1239 if (IS_R8A7791_ES2())
1240 writel(0x00000000, &axi_qos->qosconf);
1241 else
1242 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1243 writel(0x00002063, &axi_qos->qosctset0);
1244 writel(0x00000001, &axi_qos->qosreqctr);
1245 writel(0x00002064, &axi_qos->qosthres0);
1246 writel(0x00002004, &axi_qos->qosthres1);
1247 writel(0x00000001, &axi_qos->qosthres2);
1248 writel(0x00000001, &axi_qos->qosqon);
1249
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1250 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1251 writel(0x00000001, &axi_qos->qosconf);
1252 writel(0x00002073, &axi_qos->qosctset0);
1253 writel(0x00000020, &axi_qos->qosreqctr);
1254 writel(0x00002064, &axi_qos->qosthres0);
1255 writel(0x00002004, &axi_qos->qosthres1);
1256 writel(0x00000001, &axi_qos->qosthres2);
1257 writel(0x00000001, &axi_qos->qosqon);
1258
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1259 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1260 writel(0x00000001, &axi_qos->qosconf);
1261 writel(0x00002073, &axi_qos->qosctset0);
1262 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1263 if (IS_R8A7791_ES2()) {
1264 writel(0x00000001, &axi_qos->qosthres0);
1265 writel(0x00000001, &axi_qos->qosthres1);
1266 } else {
1267 writel(0x00002064, &axi_qos->qosthres0);
1268 writel(0x00002004, &axi_qos->qosthres1);
1269 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1270 writel(0x00000001, &axi_qos->qosthres2);
1271 writel(0x00000001, &axi_qos->qosqon);
1272
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1273 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1274 writel(0x00000001, &axi_qos->qosconf);
1275 writel(0x00002073, &axi_qos->qosctset0);
1276 writel(0x00000020, &axi_qos->qosreqctr);
1277 writel(0x00002064, &axi_qos->qosthres0);
1278 writel(0x00002004, &axi_qos->qosthres1);
1279 writel(0x00000001, &axi_qos->qosthres2);
1280 writel(0x00000001, &axi_qos->qosqon);
1281
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1282 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1283 writel(0x00000001, &axi_qos->qosconf);
1284 writel(0x00002073, &axi_qos->qosctset0);
1285 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1286 if (IS_R8A7791_ES2()) {
1287 writel(0x00000001, &axi_qos->qosthres0);
1288 writel(0x00000001, &axi_qos->qosthres1);
1289 } else {
1290 writel(0x00002064, &axi_qos->qosthres0);
1291 writel(0x00002004, &axi_qos->qosthres1);
1292 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1293 writel(0x00000001, &axi_qos->qosthres2);
1294 writel(0x00000001, &axi_qos->qosqon);
1295
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1296 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1297 writel(0x00000001, &axi_qos->qosconf);
1298 writel(0x00002073, &axi_qos->qosctset0);
1299 writel(0x00000020, &axi_qos->qosreqctr);
1300 writel(0x00002064, &axi_qos->qosthres0);
1301 writel(0x00002004, &axi_qos->qosthres1);
1302 writel(0x00000001, &axi_qos->qosthres2);
1303 writel(0x00000001, &axi_qos->qosqon);
1304}