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git01.mediatek.com / filogic / uboot / 95bed2d88a2626fb22e646e5fbe312910eb01f0d / . / board / renesas / blanche / qos.c
blob: f1327f6075ce98c8cbd958be4c61d2b69ad4d8d1 [file] [log] [blame]
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +0900[diff] [blame]1/*
2 * board/renesas/blanche/qos.c
3 *
4 * Copyright (C) 2016 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#include <common.h>
10#include <asm/processor.h>
11#include <asm/mach-types.h>
12#include <asm/io.h>
13#include <asm/arch/rmobile.h>
14
15#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
16enum {
17 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
18 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
19 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
20 DBSC3_15,
21 DBSC3_NR,
22};
23
24static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
25 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
26 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
27 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
28 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
29 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
30 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
31 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
32 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
33 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
34 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
35 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
36 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
37 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
38 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
39 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
40 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
41};
42
43static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
44 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
45 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
46 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
47 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
48 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
49 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
50 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
51 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
52 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
53 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
54 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
55 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
56 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
57 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
58 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
59 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
60};
61
62void qos_init(void)
63{
64 int i;
65 struct rcar_s3c *s3c;
66 struct rcar_s3c_qos *s3c_qos;
67 struct rcar_dbsc3_qos *qos_addr;
68 struct rcar_mxi *mxi;
69 struct rcar_mxi_qos *mxi_qos;
70 struct rcar_axi_qos *axi_qos;
71
72 /* DBSC DBADJ2 */
73 writel(0x20082004, DBSC3_0_DBADJ2);
74
75 /* S3C -QoS */
76 s3c = (struct rcar_s3c *)S3C_BASE;
77 // writel(0x00000000, &s3c->s3cadsplcr);
78 writel(0x1F0D0C0C, &s3c->s3crorr);
79 writel(0x1F1F0C0C, &s3c->s3cworr);
80
81 /* QoS Control Registers */
82 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
83 writel(0x00890089, &s3c_qos->s3cqos0);
84 writel(0x20960010, &s3c_qos->s3cqos1);
85 writel(0x20302030, &s3c_qos->s3cqos2);
86 writel(0x20AA2200, &s3c_qos->s3cqos3);
87 writel(0x00002032, &s3c_qos->s3cqos4);
88 writel(0x20960010, &s3c_qos->s3cqos5);
89 writel(0x20302030, &s3c_qos->s3cqos6);
90 writel(0x20AA2200, &s3c_qos->s3cqos7);
91 writel(0x00002032, &s3c_qos->s3cqos8);
92
93 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
94 writel(0x00890089, &s3c_qos->s3cqos0);
95 writel(0x20960010, &s3c_qos->s3cqos1);
96 writel(0x20302030, &s3c_qos->s3cqos2);
97 writel(0x20AA2200, &s3c_qos->s3cqos3);
98 writel(0x00002032, &s3c_qos->s3cqos4);
99 writel(0x20960010, &s3c_qos->s3cqos5);
100 writel(0x20302030, &s3c_qos->s3cqos6);
101 writel(0x20AA2200, &s3c_qos->s3cqos7);
102 writel(0x00002032, &s3c_qos->s3cqos8);
103
104 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
105 writel(0x00820082, &s3c_qos->s3cqos0);
106 writel(0x20960020, &s3c_qos->s3cqos1);
107 writel(0x20302030, &s3c_qos->s3cqos2);
108 writel(0x20AA20DC, &s3c_qos->s3cqos3);
109 writel(0x00002032, &s3c_qos->s3cqos4);
110 writel(0x20960020, &s3c_qos->s3cqos5);
111 writel(0x20302030, &s3c_qos->s3cqos6);
112 writel(0x20AA20DC, &s3c_qos->s3cqos7);
113 writel(0x00002032, &s3c_qos->s3cqos8);
114
115 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
116 writel(0x80918099, &s3c_qos->s3cqos0);
117 writel(0x20410010, &s3c_qos->s3cqos1);
118 writel(0x200A2023, &s3c_qos->s3cqos2);
119 writel(0x20502001, &s3c_qos->s3cqos3);
120 writel(0x00002032, &s3c_qos->s3cqos4);
121 writel(0x20410FFF, &s3c_qos->s3cqos5);
122 writel(0x200A2023, &s3c_qos->s3cqos6);
123 writel(0x20502001, &s3c_qos->s3cqos7);
124 writel(0x20142032, &s3c_qos->s3cqos8);
125
126 /* DBSC -QoS */
127 /* DBSC0 - Read */
128 for (i = DBSC3_00; i < DBSC3_NR; i++) {
129 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
130 writel(0x00000002, &qos_addr->dblgcnt);
131 writel(0x00002096, &qos_addr->dbtmval0);
132 writel(0x00002064, &qos_addr->dbtmval1);
133 writel(0x00002032, &qos_addr->dbtmval2);
134 writel(0x00001FB0, &qos_addr->dbtmval3);
135 writel(0x00000001, &qos_addr->dbrqctr);
136 writel(0x0000204B, &qos_addr->dbthres0);
137 writel(0x0000204B, &qos_addr->dbthres1);
138 writel(0x00001FC4, &qos_addr->dbthres2);
139 writel(0x00000001, &qos_addr->dblgqon);
140 }
141
142 /* DBSC0 - Write */
143 for (i = DBSC3_00; i < DBSC3_NR; i++) {
144 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
145 writel(0x00000002, &qos_addr->dblgcnt);
146 writel(0x00002096, &qos_addr->dbtmval0);
147 writel(0x0000206E, &qos_addr->dbtmval1);
148 writel(0x00002050, &qos_addr->dbtmval2);
149 writel(0x0000203A, &qos_addr->dbtmval3);
150 writel(0x00000001, &qos_addr->dbrqctr);
151 writel(0x0000205A, &qos_addr->dbthres0);
152 writel(0x0000205A, &qos_addr->dbthres1);
153 writel(0x0000203C, &qos_addr->dbthres2);
154 writel(0x00000001, &qos_addr->dblgqon);
155 }
156
157 /* MXI -QoS */
158 /* Transaction Control (MXI) */
159 mxi = (struct rcar_mxi *)MXI_BASE;
160 writel(0x00000100, &mxi->mxaxirtcr);
161 writel(0xFF530100, &mxi->mxaxiwtcr);
162 writel(0x00000100, &mxi->mxs3crtcr);
163 writel(0xFF530100, &mxi->mxs3cwtcr);
164 writel(0x004000C0, &mxi->mxsaar0);
165 writel(0x02000800, &mxi->mxsaar1);
166
167 /* QoS Control (MXI) */
168 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
169 writel(0x0000000C, &mxi_qos->du0);
170
171 /* AXI -QoS */
172 /* Transaction Control (MXI) */
173 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
174 writel(0x00000102, &axi_qos->qosconf);
175 writel(0x0000205F, &axi_qos->qosctset0);
176 writel(0x00000001, &axi_qos->qosreqctr);
177 writel(0x00000001, &axi_qos->qosqon);
178
179 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
180 writel(0x00000100, &axi_qos->qosconf);
181 writel(0x00002053, &axi_qos->qosctset0);
182 writel(0x00000001, &axi_qos->qosreqctr);
183 writel(0x00000001, &axi_qos->qosqon);
184 writel(0x00000005, &axi_qos->qosin);
185
186 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
187 writel(0x00000100, &axi_qos->qosconf);
188 writel(0x00002029, &axi_qos->qosctset0);
189 writel(0x00000001, &axi_qos->qosreqctr);
190 writel(0x00000001, &axi_qos->qosqon);
191 writel(0x00000005, &axi_qos->qosin);
192
193 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
194 writel(0x00000102, &axi_qos->qosconf);
195 writel(0x0000205F, &axi_qos->qosctset0);
196 writel(0x00000001, &axi_qos->qosreqctr);
197 writel(0x00000001, &axi_qos->qosqon);
198 writel(0x00000005, &axi_qos->qosin);
199
200 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
201 writel(0x00000100, &axi_qos->qosconf);
202 writel(0x00002053, &axi_qos->qosctset0);
203 writel(0x00000001, &axi_qos->qosreqctr);
204 writel(0x00000001, &axi_qos->qosqon);
205 writel(0x00000005, &axi_qos->qosin);
206
207 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
208 writel(0x00000100, &axi_qos->qosconf);
209 writel(0x000020A6, &axi_qos->qosctset0);
210 writel(0x00000001, &axi_qos->qosreqctr);
211 writel(0x00000001, &axi_qos->qosqon);
212 writel(0x00000005, &axi_qos->qosin);
213
214 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
215 writel(0x00000100, &axi_qos->qosconf);
216 writel(0x000020A6, &axi_qos->qosctset0);
217 writel(0x00000001, &axi_qos->qosreqctr);
218 writel(0x00000001, &axi_qos->qosqon);
219 writel(0x00000005, &axi_qos->qosin);
220
221 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
222 writel(0x00000102, &axi_qos->qosconf);
223 writel(0x0000205F, &axi_qos->qosctset0);
224 writel(0x00000001, &axi_qos->qosreqctr);
225 writel(0x00000001, &axi_qos->qosqon);
226
227 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
228 writel(0x00000102, &axi_qos->qosconf);
229 writel(0x0000205F, &axi_qos->qosctset0);
230 writel(0x00000001, &axi_qos->qosreqctr);
231 writel(0x00000001, &axi_qos->qosqon);
232
233 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
234 writel(0x00000100, &axi_qos->qosconf);
235 writel(0x0000214C, &axi_qos->qosctset0);
236 writel(0x00000001, &axi_qos->qosreqctr);
237 writel(0x00000001, &axi_qos->qosqon);
238 writel(0x00000005, &axi_qos->qosin);
239
240 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
241 writel(0x00000101, &axi_qos->qosconf);
242 writel(0x00002008, &axi_qos->qosctset0);
243 writel(0x00000010, &axi_qos->qosreqctr);
244 writel(0x00000001, &axi_qos->qosqon);
245
246 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
247 writel(0x00000101, &axi_qos->qosconf);
248 writel(0x00002008, &axi_qos->qosctset0);
249 writel(0x00000010, &axi_qos->qosreqctr);
250 writel(0x00000001, &axi_qos->qosqon);
251
252 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
253 writel(0x00000101, &axi_qos->qosconf);
254 writel(0x00002008, &axi_qos->qosctset0);
255 writel(0x00000010, &axi_qos->qosreqctr);
256 writel(0x00000001, &axi_qos->qosqon);
257
258 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
259 writel(0x00000101, &axi_qos->qosconf);
260 writel(0x00002008, &axi_qos->qosctset0);
261 writel(0x00000010, &axi_qos->qosreqctr);
262 writel(0x00000001, &axi_qos->qosqon);
263
264 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
265 writel(0x00000102, &axi_qos->qosconf);
266 writel(0x0000205F, &axi_qos->qosctset0);
267 writel(0x00000001, &axi_qos->qosreqctr);
268 writel(0x00000001, &axi_qos->qosqon);
269
270 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
271 writel(0x00000000, &axi_qos->qosconf);
272 writel(0x0000214C, &axi_qos->qosctset0);
273 writel(0x00000001, &axi_qos->qosreqctr);
274 writel(0x00000001, &axi_qos->qosqon);
275
276 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
277 writel(0x00000000, &axi_qos->qosconf);
278 writel(0x0000214C, &axi_qos->qosctset0);
279 writel(0x00000001, &axi_qos->qosreqctr);
280 writel(0x00000001, &axi_qos->qosqon);
281 writel(0x00000005, &axi_qos->qosin);
282
283 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
284 writel(0x00000000, &axi_qos->qosconf);
285 writel(0x0000214C, &axi_qos->qosctset0);
286 writel(0x00000001, &axi_qos->qosreqctr);
287 writel(0x00000001, &axi_qos->qosqon);
288 writel(0x00000005, &axi_qos->qosin);
289
290 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
291 writel(0x00000000, &axi_qos->qosconf);
292 writel(0x0000214C, &axi_qos->qosctset0);
293 writel(0x00000001, &axi_qos->qosreqctr);
294 writel(0x00000001, &axi_qos->qosqon);
295 writel(0x00000005, &axi_qos->qosin);
296
297 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
298 writel(0x00000100, &axi_qos->qosconf);
299 writel(0x000020A6, &axi_qos->qosctset0);
300 writel(0x00000001, &axi_qos->qosreqctr);
301 writel(0x00000001, &axi_qos->qosqon);
302 writel(0x00000005, &axi_qos->qosin);
303
304 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
305 writel(0x00000100, &axi_qos->qosconf);
306 writel(0x0000214C, &axi_qos->qosctset0);
307 writel(0x00000001, &axi_qos->qosreqctr);
308 writel(0x00000001, &axi_qos->qosqon);
309 writel(0x00000005, &axi_qos->qosin);
310
311 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
312 writel(0x00000101, &axi_qos->qosconf);
313 writel(0x0000214C, &axi_qos->qosctset0);
314 writel(0x00000020, &axi_qos->qosreqctr);
315 writel(0x00000001, &axi_qos->qosqon);
316 writel(0x00000005, &axi_qos->qosin);
317
318 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
319 writel(0x00002041, &axi_qos->qosctset1);
320 writel(0x00002023, &axi_qos->qosctset2);
321 writel(0x0000200A, &axi_qos->qosctset3);
322 writel(0x00002050, &axi_qos->qosthres0);
323 writel(0x00002032, &axi_qos->qosthres1);
324 writel(0x00002014, &axi_qos->qosthres2);
325
326 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
327 writel(0x00000102, &axi_qos->qosconf);
328 writel(0x0000205F, &axi_qos->qosctset0);
329 writel(0x00000001, &axi_qos->qosreqctr);
330 writel(0x00000001, &axi_qos->qosqon);
331
332 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
333 writel(0x00000100, &axi_qos->qosconf);
334 writel(0x00002053, &axi_qos->qosctset0);
335 writel(0x00000001, &axi_qos->qosreqctr);
336 writel(0x00000001, &axi_qos->qosqon);
337 writel(0x00000005, &axi_qos->qosin);
338
339 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
340 writel(0x00000100, &axi_qos->qosconf);
341 writel(0x00002029, &axi_qos->qosctset0);
342 writel(0x00000001, &axi_qos->qosreqctr);
343 writel(0x00000001, &axi_qos->qosqon);
344 writel(0x00000005, &axi_qos->qosin);
345
346 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
347 writel(0x00000102, &axi_qos->qosconf);
348 writel(0x0000205F, &axi_qos->qosctset0);
349 writel(0x00000001, &axi_qos->qosreqctr);
350 writel(0x00000001, &axi_qos->qosqon);
351 writel(0x00000005, &axi_qos->qosin);
352
353 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
354 writel(0x00000100, &axi_qos->qosconf);
355 writel(0x00002053, &axi_qos->qosctset0);
356 writel(0x00000001, &axi_qos->qosreqctr);
357 writel(0x00000001, &axi_qos->qosqon);
358 writel(0x00000005, &axi_qos->qosin);
359
360 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
361 writel(0x00000100, &axi_qos->qosconf);
362 writel(0x000020A6, &axi_qos->qosctset0);
363 writel(0x00000001, &axi_qos->qosreqctr);
364 writel(0x00000001, &axi_qos->qosqon);
365 writel(0x00000005, &axi_qos->qosin);
366
367 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
368 writel(0x00000102, &axi_qos->qosconf);
369 writel(0x0000205F, &axi_qos->qosctset0);
370 writel(0x00000001, &axi_qos->qosreqctr);
371 writel(0x00000001, &axi_qos->qosqon);
372
373 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
374 writel(0x00000102, &axi_qos->qosconf);
375 writel(0x0000205F, &axi_qos->qosctset0);
376 writel(0x00000001, &axi_qos->qosreqctr);
377 writel(0x00000001, &axi_qos->qosqon);
378
379 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
380 writel(0x00000102, &axi_qos->qosconf);
381 writel(0x0000205F, &axi_qos->qosctset0);
382 writel(0x00000001, &axi_qos->qosreqctr);
383 writel(0x00000001, &axi_qos->qosqon);
384
385 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
386 writel(0x00000100, &axi_qos->qosconf);
387 writel(0x0000214C, &axi_qos->qosctset0);
388 writel(0x00000001, &axi_qos->qosreqctr);
389 writel(0x00000001, &axi_qos->qosqon);
390 writel(0x00000005, &axi_qos->qosin);
391
392 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
393 writel(0x00000102, &axi_qos->qosconf);
394 writel(0x0000205F, &axi_qos->qosctset0);
395 writel(0x00000001, &axi_qos->qosreqctr);
396 writel(0x00000001, &axi_qos->qosqon);
397
398 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
399 writel(0x00000000, &axi_qos->qosconf);
400 writel(0x0000214C, &axi_qos->qosctset0);
401 writel(0x00000001, &axi_qos->qosreqctr);
402 writel(0x00000001, &axi_qos->qosqon);
403 writel(0x00000005, &axi_qos->qosin);
404
405 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
406 writel(0x00000000, &axi_qos->qosconf);
407 writel(0x0000214C, &axi_qos->qosctset0);
408 writel(0x00000001, &axi_qos->qosreqctr);
409 writel(0x00000001, &axi_qos->qosqon);
410 writel(0x00000005, &axi_qos->qosin);
411
412 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
413 writel(0x00000000, &axi_qos->qosconf);
414 writel(0x0000214C, &axi_qos->qosctset0);
415 writel(0x00000001, &axi_qos->qosreqctr);
416 writel(0x00000001, &axi_qos->qosqon);
417 writel(0x00000005, &axi_qos->qosin);
418
419 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
420 writel(0x00000000, &axi_qos->qosconf);
421 writel(0x0000214C, &axi_qos->qosctset0);
422 writel(0x00000001, &axi_qos->qosreqctr);
423 writel(0x00000001, &axi_qos->qosqon);
424 writel(0x00000005, &axi_qos->qosin);
425
426 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
427 writel(0x00000100, &axi_qos->qosconf);
428 writel(0x000020A6, &axi_qos->qosctset0);
429 writel(0x00000001, &axi_qos->qosreqctr);
430 writel(0x00000001, &axi_qos->qosqon);
431 writel(0x00000005, &axi_qos->qosin);
432
433 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
434 writel(0x00000100, &axi_qos->qosconf);
435 writel(0x0000214C, &axi_qos->qosctset0);
436 writel(0x00000001, &axi_qos->qosreqctr);
437 writel(0x00000001, &axi_qos->qosqon);
438 writel(0x00000005, &axi_qos->qosin);
439
440 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
441 writel(0x00000101, &axi_qos->qosconf);
442 writel(0x0000214C, &axi_qos->qosctset0);
443 writel(0x00000020, &axi_qos->qosreqctr);
444 writel(0x00000001, &axi_qos->qosqon);
445 writel(0x00000005, &axi_qos->qosin);
446
447 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
448 writel(0x00002041, &axi_qos->qosctset1);
449 writel(0x00002023, &axi_qos->qosctset2);
450 writel(0x0000200A, &axi_qos->qosctset3);
451 writel(0x00002050, &axi_qos->qosthres0);
452 writel(0x00002032, &axi_qos->qosthres1);
453 writel(0x00002014, &axi_qos->qosthres2);
454
455 /* QoS Register (SYS-AXI256) */
456 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
457 writel(0x00000102, &axi_qos->qosconf);
458 writel(0x0000205F, &axi_qos->qosctset0);
459 writel(0x00000001, &axi_qos->qosreqctr);
460 writel(0x00000001, &axi_qos->qosqon);
461
462 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
463 writel(0x00000102, &axi_qos->qosconf);
464 writel(0x0000205F, &axi_qos->qosctset0);
465 writel(0x00000001, &axi_qos->qosreqctr);
466 writel(0x00000001, &axi_qos->qosqon);
467
468 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
469 writel(0x00000102, &axi_qos->qosconf);
470 writel(0x0000205F, &axi_qos->qosctset0);
471 writel(0x00000001, &axi_qos->qosreqctr);
472 writel(0x00000001, &axi_qos->qosqon);
473
474 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
475 writel(0x00000100, &axi_qos->qosconf);
476 writel(0x0000211B, &axi_qos->qosctset0);
477 writel(0x00000001, &axi_qos->qosreqctr);
478 writel(0x00000001, &axi_qos->qosqon);
479 writel(0x00000005, &axi_qos->qosin);
480
481 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
482 writel(0x00002041, &axi_qos->qosctset1);
483 writel(0x00002023, &axi_qos->qosctset2);
484 writel(0x0000200A, &axi_qos->qosctset3);
485 writel(0x00002050, &axi_qos->qosthres0);
486 writel(0x00002032, &axi_qos->qosthres1);
487 writel(0x00002014, &axi_qos->qosthres2);
488
489 axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
490 writel(0x00000102, &axi_qos->qosconf);
491 writel(0x0000205F, &axi_qos->qosctset0);
492 writel(0x00000001, &axi_qos->qosreqctr);
493 writel(0x00000001, &axi_qos->qosqon);
494
495 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
496 writel(0x00000102, &axi_qos->qosconf);
497 writel(0x0000205F, &axi_qos->qosctset0);
498 writel(0x00000001, &axi_qos->qosreqctr);
499 writel(0x00000001, &axi_qos->qosqon);
500
501 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
502 writel(0x00000102, &axi_qos->qosconf);
503 writel(0x0000205F, &axi_qos->qosctset0);
504 writel(0x00000001, &axi_qos->qosreqctr);
505 writel(0x00000001, &axi_qos->qosqon);
506
507 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
508 writel(0x00000100, &axi_qos->qosconf);
509 writel(0x00002029, &axi_qos->qosctset0);
510 writel(0x00000001, &axi_qos->qosreqctr);
511 writel(0x00000001, &axi_qos->qosqon);
512 writel(0x00000005, &axi_qos->qosin);
513
514 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
515 writel(0x00002041, &axi_qos->qosctset1);
516 writel(0x00002023, &axi_qos->qosctset2);
517 writel(0x0000200A, &axi_qos->qosctset3);
518 writel(0x00002050, &axi_qos->qosthres0);
519 writel(0x00002032, &axi_qos->qosthres1);
520 writel(0x00002014, &axi_qos->qosthres2);
521
522 /* QoS Register (RT-AXI) */
523 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
524 writel(0x00000000, &axi_qos->qosconf);
525 writel(0x00002055, &axi_qos->qosctset0);
526 writel(0x00000000, &axi_qos->qosreqctr);
527 writel(0x00000000, &axi_qos->qosqon);
528
529 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
530 writel(0x00000000, &axi_qos->qosconf);
531 writel(0x00002055, &axi_qos->qosctset0);
532 writel(0x00000000, &axi_qos->qosreqctr);
533 writel(0x00000000, &axi_qos->qosqon);
534
535 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
536 writel(0x00000000, &axi_qos->qosconf);
537 writel(0x00002001, &axi_qos->qosctset0);
538 writel(0x00000000, &axi_qos->qosreqctr);
539 writel(0x00000000, &axi_qos->qosqon);
540
541 axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
542 writel(0x00002001, &axi_qos->qosctset1);
543 writel(0x00002001, &axi_qos->qosctset2);
544 writel(0x00002001, &axi_qos->qosctset3);
545 writel(0x00000000, &axi_qos->qosthres0);
546 writel(0x00000000, &axi_qos->qosthres1);
547 writel(0x00000000, &axi_qos->qosthres2);
548
549 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
550 writel(0x00000000, &axi_qos->qosconf);
551 writel(0x00002055, &axi_qos->qosctset0);
552 writel(0x00000000, &axi_qos->qosreqctr);
553 writel(0x00000000, &axi_qos->qosqon);
554
555 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
556 writel(0x00000000, &axi_qos->qosconf);
557 writel(0x00002055, &axi_qos->qosctset0);
558 writel(0x00000000, &axi_qos->qosreqctr);
559 writel(0x00000000, &axi_qos->qosqon);
560
561 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
562 writel(0x00000000, &axi_qos->qosconf);
563 writel(0x00002001, &axi_qos->qosctset0);
564 writel(0x00000000, &axi_qos->qosreqctr);
565 writel(0x00000000, &axi_qos->qosqon);
566
567 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
568 writel(0x00002001, &axi_qos->qosctset1);
569 writel(0x00002001, &axi_qos->qosctset2);
570 writel(0x00002001, &axi_qos->qosctset3);
571 writel(0x00000000, &axi_qos->qosthres0);
572 writel(0x00000000, &axi_qos->qosthres1);
573 writel(0x00000000, &axi_qos->qosthres2);
574
575 /* QoS Register (CCI-AXI) */
576 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
577 writel(0x00000101, &axi_qos->qosconf);
578 writel(0x00002008, &axi_qos->qosctset0);
579 writel(0x00002041, &axi_qos->qosctset1);
580 writel(0x00002023, &axi_qos->qosctset2);
581 writel(0x0000200A, &axi_qos->qosctset3);
582 writel(0x00000010, &axi_qos->qosreqctr);
583 writel(0x00002050, &axi_qos->qosthres0);
584 writel(0x00002032, &axi_qos->qosthres1);
585 writel(0x00002014, &axi_qos->qosthres2);
586 writel(0x00000001, &axi_qos->qosqon);
587
588 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
589 writel(0x00000102, &axi_qos->qosconf);
590 writel(0x0000205F, &axi_qos->qosctset0);
591 writel(0x00002041, &axi_qos->qosctset1);
592 writel(0x00002023, &axi_qos->qosctset2);
593 writel(0x0000200A, &axi_qos->qosctset3);
594 writel(0x00000001, &axi_qos->qosreqctr);
595 writel(0x00002050, &axi_qos->qosthres0);
596 writel(0x00002032, &axi_qos->qosthres1);
597 writel(0x00002014, &axi_qos->qosthres2);
598 writel(0x00000001, &axi_qos->qosqon);
599
600 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
601 writel(0x00000101, &axi_qos->qosconf);
602 writel(0x00002008, &axi_qos->qosctset0);
603 writel(0x00002041, &axi_qos->qosctset1);
604 writel(0x00002023, &axi_qos->qosctset2);
605 writel(0x0000000A, &axi_qos->qosctset3);
606 writel(0x00000010, &axi_qos->qosreqctr);
607 writel(0x00002050, &axi_qos->qosthres0);
608 writel(0x00002032, &axi_qos->qosthres1);
609 writel(0x00002018, &axi_qos->qosthres2);
610 writel(0x00000001, &axi_qos->qosqon);
611
612 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
613 writel(0x00000101, &axi_qos->qosconf);
614 writel(0x00002008, &axi_qos->qosctset0);
615 writel(0x00002041, &axi_qos->qosctset1);
616 writel(0x00002023, &axi_qos->qosctset2);
617 writel(0x0000200A, &axi_qos->qosctset3);
618 writel(0x00000010, &axi_qos->qosreqctr);
619 writel(0x00002050, &axi_qos->qosthres0);
620 writel(0x00002032, &axi_qos->qosthres1);
621 writel(0x00002014, &axi_qos->qosthres2);
622 writel(0x00000001, &axi_qos->qosqon);
623
624 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
625 writel(0x00000101, &axi_qos->qosconf);
626 writel(0x00002008, &axi_qos->qosctset0);
627 writel(0x00002041, &axi_qos->qosctset1);
628 writel(0x00002023, &axi_qos->qosctset2);
629 writel(0x0000200A, &axi_qos->qosctset3);
630 writel(0x00000010, &axi_qos->qosreqctr);
631 writel(0x00002050, &axi_qos->qosthres0);
632 writel(0x00002032, &axi_qos->qosthres1);
633 writel(0x00002014, &axi_qos->qosthres2);
634 writel(0x00000001, &axi_qos->qosqon);
635
636 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
637 writel(0x00000102, &axi_qos->qosconf);
638 writel(0x0000205F, &axi_qos->qosctset0);
639 writel(0x00002041, &axi_qos->qosctset1);
640 writel(0x00002023, &axi_qos->qosctset2);
641 writel(0x0000200A, &axi_qos->qosctset3);
642 writel(0x00000001, &axi_qos->qosreqctr);
643 writel(0x00002050, &axi_qos->qosthres0);
644 writel(0x00002032, &axi_qos->qosthres1);
645 writel(0x00002014, &axi_qos->qosthres2);
646 writel(0x00000001, &axi_qos->qosqon);
647
648 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
649 writel(0x00000101, &axi_qos->qosconf);
650 writel(0x00002008, &axi_qos->qosctset0);
651 writel(0x00002041, &axi_qos->qosctset1);
652 writel(0x00002023, &axi_qos->qosctset2);
653 writel(0x0000200A, &axi_qos->qosctset3);
654 writel(0x00000001, &axi_qos->qosreqctr);
655 writel(0x00002050, &axi_qos->qosthres0);
656 writel(0x00002032, &axi_qos->qosthres1);
657 writel(0x00002014, &axi_qos->qosthres2);
658 writel(0x00000001, &axi_qos->qosqon);
659
660 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
661 writel(0x00000101, &axi_qos->qosconf);
662 writel(0x00002008, &axi_qos->qosctset0);
663 writel(0x00002041, &axi_qos->qosctset1);
664 writel(0x00002023, &axi_qos->qosctset2);
665 writel(0x0000200A, &axi_qos->qosctset3);
666 writel(0x00000010, &axi_qos->qosreqctr);
667 writel(0x00002050, &axi_qos->qosthres0);
668 writel(0x00002032, &axi_qos->qosthres1);
669 writel(0x00002014, &axi_qos->qosthres2);
670 writel(0x00000001, &axi_qos->qosqon);
671
672 /* QoS Register (Media-AXI) */
673 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
674 writel(0x00000102, &axi_qos->qosconf);
675 writel(0x000020DC, &axi_qos->qosctset0);
676 writel(0x00002096, &axi_qos->qosctset1);
677 writel(0x00002030, &axi_qos->qosctset2);
678 writel(0x00002030, &axi_qos->qosctset3);
679 writel(0x00000020, &axi_qos->qosreqctr);
680 writel(0x000020AA, &axi_qos->qosthres0);
681 writel(0x00002032, &axi_qos->qosthres1);
682 writel(0x00000001, &axi_qos->qosthres2);
683
684 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
685 writel(0x00000102, &axi_qos->qosconf);
686 writel(0x000020DC, &axi_qos->qosctset0);
687 writel(0x00002096, &axi_qos->qosctset1);
688 writel(0x00002030, &axi_qos->qosctset2);
689 writel(0x00002030, &axi_qos->qosctset3);
690 writel(0x00000020, &axi_qos->qosreqctr);
691 writel(0x000020AA, &axi_qos->qosthres0);
692 writel(0x00002032, &axi_qos->qosthres1);
693 writel(0x00000001, &axi_qos->qosthres2);
694
695 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
696 writel(0x00000001, &axi_qos->qosconf);
697 writel(0x00002018, &axi_qos->qosctset0);
698 writel(0x00000020, &axi_qos->qosreqctr);
699 writel(0x00002006, &axi_qos->qosthres0);
700 writel(0x00002001, &axi_qos->qosthres1);
701 writel(0x00000001, &axi_qos->qosthres2);
702 writel(0x00000001, &axi_qos->qosqon);
703
704 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
705 writel(0x00000100, &axi_qos->qosconf);
706 writel(0x00002259, &axi_qos->qosctset0);
707 writel(0x00000001, &axi_qos->qosreqctr);
708 writel(0x00002050, &axi_qos->qosthres0);
709 writel(0x00002032, &axi_qos->qosthres1);
710 writel(0x00002014, &axi_qos->qosthres2);
711 writel(0x00000001, &axi_qos->qosqon);
712
713 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
714 writel(0x00000100, &axi_qos->qosconf);
715 writel(0x00002053, &axi_qos->qosctset0);
716 writel(0x00000001, &axi_qos->qosreqctr);
717 writel(0x00002050, &axi_qos->qosthres0);
718 writel(0x00002032, &axi_qos->qosthres1);
719 writel(0x00002014, &axi_qos->qosthres2);
720 writel(0x00000001, &axi_qos->qosqon);
721
722 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
723 writel(0x00000100, &axi_qos->qosconf);
724 writel(0x00002053, &axi_qos->qosctset0);
725 writel(0x00000001, &axi_qos->qosreqctr);
726 writel(0x00002050, &axi_qos->qosthres0);
727 writel(0x00002032, &axi_qos->qosthres1);
728 writel(0x00002014, &axi_qos->qosthres2);
729 writel(0x00000001, &axi_qos->qosqon);
730
731 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
732 writel(0x00000100, &axi_qos->qosconf);
733 writel(0x00002053, &axi_qos->qosctset0);
734 writel(0x00000001, &axi_qos->qosreqctr);
735 writel(0x00002050, &axi_qos->qosthres0);
736 writel(0x00002032, &axi_qos->qosthres1);
737 writel(0x00002014, &axi_qos->qosthres2);
738 writel(0x00000001, &axi_qos->qosqon);
739
740 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
741 writel(0x00000100, &axi_qos->qosconf);
742 writel(0x00002053, &axi_qos->qosctset0);
743 writel(0x00000001, &axi_qos->qosreqctr);
744 writel(0x00002050, &axi_qos->qosthres0);
745 writel(0x00002032, &axi_qos->qosthres1);
746 writel(0x00002014, &axi_qos->qosthres2);
747 writel(0x00000001, &axi_qos->qosqon);
748
749 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
750 writel(0x00000100, &axi_qos->qosconf);
751 writel(0x00002053, &axi_qos->qosctset0);
752 writel(0x00000001, &axi_qos->qosreqctr);
753 writel(0x00002050, &axi_qos->qosthres0);
754 writel(0x00002032, &axi_qos->qosthres1);
755 writel(0x00002014, &axi_qos->qosthres2);
756 writel(0x00000001, &axi_qos->qosqon);
757
758 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
759 writel(0x00000100, &axi_qos->qosconf);
760 writel(0x00002053, &axi_qos->qosctset0);
761 writel(0x00000001, &axi_qos->qosreqctr);
762 writel(0x00002050, &axi_qos->qosthres0);
763 writel(0x00002032, &axi_qos->qosthres1);
764 writel(0x00002014, &axi_qos->qosthres2);
765 writel(0x00000001, &axi_qos->qosqon);
766
767 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
768 writel(0x00000101, &axi_qos->qosconf);
769 writel(0x00002046, &axi_qos->qosctset0);
770 writel(0x00000020, &axi_qos->qosreqctr);
771 writel(0x00002050, &axi_qos->qosthres0);
772 writel(0x00002032, &axi_qos->qosthres1);
773 writel(0x00002014, &axi_qos->qosthres2);
774 writel(0x00000001, &axi_qos->qosqon);
775
776 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
777 writel(0x00000101, &axi_qos->qosconf);
778 writel(0x00002046, &axi_qos->qosctset0);
779 writel(0x00000020, &axi_qos->qosreqctr);
780 writel(0x00002050, &axi_qos->qosthres0);
781 writel(0x00002032, &axi_qos->qosthres1);
782 writel(0x00002014, &axi_qos->qosthres2);
783 writel(0x00000001, &axi_qos->qosqon);
784
785 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
786 writel(0x00000101, &axi_qos->qosconf);
787 writel(0x000020D0, &axi_qos->qosctset0);
788 writel(0x00000020, &axi_qos->qosreqctr);
789 writel(0x00002050, &axi_qos->qosthres0);
790 writel(0x00002032, &axi_qos->qosthres1);
791 writel(0x00002014, &axi_qos->qosthres2);
792 writel(0x00000001, &axi_qos->qosqon);
793
794 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
795 writel(0x00000101, &axi_qos->qosconf);
796 writel(0x00002034, &axi_qos->qosctset0);
797 writel(0x0000000C, &axi_qos->qosreqctr);
798 writel(0x00002050, &axi_qos->qosthres0);
799 writel(0x00002032, &axi_qos->qosthres1);
800 writel(0x00002014, &axi_qos->qosthres2);
801 writel(0x00000001, &axi_qos->qosqon);
802
803 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
804 writel(0x00000101, &axi_qos->qosconf);
805 writel(0x0000200D, &axi_qos->qosctset0);
806 writel(0x000000C0, &axi_qos->qosreqctr);
807 writel(0x00002050, &axi_qos->qosthres0);
808 writel(0x00002032, &axi_qos->qosthres1);
809 writel(0x00002014, &axi_qos->qosthres2);
810 writel(0x00000001, &axi_qos->qosqon);
811
812 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
813 writel(0x00000101, &axi_qos->qosconf);
814 writel(0x00002034, &axi_qos->qosctset0);
815 writel(0x0000000C, &axi_qos->qosreqctr);
816 writel(0x00002050, &axi_qos->qosthres0);
817 writel(0x00002032, &axi_qos->qosthres1);
818 writel(0x00002014, &axi_qos->qosthres2);
819 writel(0x00000001, &axi_qos->qosqon);
820
821 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
822 writel(0x00000101, &axi_qos->qosconf);
823 writel(0x0000200D, &axi_qos->qosctset0);
824 writel(0x000000C0, &axi_qos->qosreqctr);
825 writel(0x00002050, &axi_qos->qosthres0);
826 writel(0x00002032, &axi_qos->qosthres1);
827 writel(0x00002014, &axi_qos->qosthres2);
828 writel(0x00000001, &axi_qos->qosqon);
829
830 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
831 writel(0x00000101, &axi_qos->qosconf);
832 writel(0x00002034, &axi_qos->qosctset0);
833 writel(0x0000000C, &axi_qos->qosreqctr);
834 writel(0x00002050, &axi_qos->qosthres0);
835 writel(0x00002032, &axi_qos->qosthres1);
836 writel(0x00002014, &axi_qos->qosthres2);
837 writel(0x00000001, &axi_qos->qosqon);
838
839 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
840 writel(0x00000101, &axi_qos->qosconf);
841 writel(0x0000200D, &axi_qos->qosctset0);
842 writel(0x000000C0, &axi_qos->qosreqctr);
843 writel(0x00002050, &axi_qos->qosthres0);
844 writel(0x00002032, &axi_qos->qosthres1);
845 writel(0x00002014, &axi_qos->qosthres2);
846 writel(0x00000001, &axi_qos->qosqon);
847
848 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
849 writel(0x00000100, &axi_qos->qosconf);
850 writel(0x00002069, &axi_qos->qosctset0);
851 writel(0x00000001, &axi_qos->qosreqctr);
852 writel(0x00002050, &axi_qos->qosthres0);
853 writel(0x00002032, &axi_qos->qosthres1);
854 writel(0x00002014, &axi_qos->qosthres2);
855 writel(0x00000001, &axi_qos->qosqon);
856
857 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
858 writel(0x00000100, &axi_qos->qosconf);
859 writel(0x00002069, &axi_qos->qosctset0);
860 writel(0x00000001, &axi_qos->qosreqctr);
861 writel(0x00002050, &axi_qos->qosthres0);
862 writel(0x00002032, &axi_qos->qosthres1);
863 writel(0x00002014, &axi_qos->qosthres2);
864 writel(0x00000001, &axi_qos->qosqon);
865
866 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
867 writel(0x00000100, &axi_qos->qosconf);
868 writel(0x0000204C, &axi_qos->qosctset0);
869 writel(0x00000001, &axi_qos->qosreqctr);
870 writel(0x00002050, &axi_qos->qosthres0);
871 writel(0x00002032, &axi_qos->qosthres1);
872 writel(0x00002014, &axi_qos->qosthres2);
873 writel(0x00000001, &axi_qos->qosqon);
874
875 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
876 writel(0x00000100, &axi_qos->qosconf);
877 writel(0x00002200, &axi_qos->qosctset0);
878 writel(0x00000001, &axi_qos->qosreqctr);
879 writel(0x00002050, &axi_qos->qosthres0);
880 writel(0x00002032, &axi_qos->qosthres1);
881 writel(0x00002014, &axi_qos->qosthres2);
882 writel(0x00000001, &axi_qos->qosqon);
883
884 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
885 writel(0x00000100, &axi_qos->qosconf);
886 writel(0x00002455, &axi_qos->qosctset0);
887 writel(0x00000001, &axi_qos->qosreqctr);
888 writel(0x00002050, &axi_qos->qosthres0);
889 writel(0x00002032, &axi_qos->qosthres1);
890 writel(0x00002014, &axi_qos->qosthres2);
891 writel(0x00000001, &axi_qos->qosqon);
892
893 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
894 writel(0x00000100, &axi_qos->qosconf);
895 writel(0x00002455, &axi_qos->qosctset0);
896 writel(0x00000001, &axi_qos->qosreqctr);
897 writel(0x00002050, &axi_qos->qosthres0);
898 writel(0x00002032, &axi_qos->qosthres1);
899 writel(0x00002014, &axi_qos->qosthres2);
900 writel(0x00000001, &axi_qos->qosqon);
901
902 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
903 writel(0x00000101, &axi_qos->qosconf);
904 writel(0x00002034, &axi_qos->qosctset0);
905 writel(0x00000008, &axi_qos->qosreqctr);
906 writel(0x00002050, &axi_qos->qosthres0);
907 writel(0x00002032, &axi_qos->qosthres1);
908 writel(0x00002014, &axi_qos->qosthres2);
909 writel(0x00000001, &axi_qos->qosqon);
910
911 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
912 writel(0x00000101, &axi_qos->qosconf);
913 writel(0x000020D3, &axi_qos->qosctset0);
914 writel(0x00000008, &axi_qos->qosreqctr);
915 writel(0x00002050, &axi_qos->qosthres0);
916 writel(0x00002032, &axi_qos->qosthres1);
917 writel(0x00002014, &axi_qos->qosthres2);
918 writel(0x00000001, &axi_qos->qosqon);
919
920 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
921 writel(0x00000101, &axi_qos->qosconf);
922 writel(0x00002034, &axi_qos->qosctset0);
923 writel(0x00000008, &axi_qos->qosreqctr);
924 writel(0x00002050, &axi_qos->qosthres0);
925 writel(0x00002032, &axi_qos->qosthres1);
926 writel(0x00002014, &axi_qos->qosthres2);
927 writel(0x00000001, &axi_qos->qosqon);
928
929 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
930 writel(0x00000101, &axi_qos->qosconf);
931 writel(0x000020D3, &axi_qos->qosctset0);
932 writel(0x00000008, &axi_qos->qosreqctr);
933 writel(0x00002050, &axi_qos->qosthres0);
934 writel(0x00002032, &axi_qos->qosthres1);
935 writel(0x00002014, &axi_qos->qosthres2);
936 writel(0x00000001, &axi_qos->qosqon);
937
938 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
939 writel(0x00000101, &axi_qos->qosconf);
940 writel(0x0000201A, &axi_qos->qosctset0);
941 writel(0x00000018, &axi_qos->qosreqctr);
942 writel(0x00002050, &axi_qos->qosthres0);
943 writel(0x00002032, &axi_qos->qosthres1);
944 writel(0x00002014, &axi_qos->qosthres2);
945 writel(0x00000001, &axi_qos->qosqon);
946
947 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
948 writel(0x00000101, &axi_qos->qosconf);
949 writel(0x00002006, &axi_qos->qosctset0);
950 writel(0x00000018, &axi_qos->qosreqctr);
951 writel(0x00002050, &axi_qos->qosthres0);
952 writel(0x00002032, &axi_qos->qosthres1);
953 writel(0x00002014, &axi_qos->qosthres2);
954 writel(0x00000001, &axi_qos->qosqon);
955
956 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
957 writel(0x00000100, &axi_qos->qosconf);
958 writel(0x0000201A, &axi_qos->qosctset0);
959 writel(0x00000001, &axi_qos->qosreqctr);
960 writel(0x00002050, &axi_qos->qosthres0);
961 writel(0x00002032, &axi_qos->qosthres1);
962 writel(0x00002014, &axi_qos->qosthres2);
963 writel(0x00000001, &axi_qos->qosqon);
964
965 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
966 writel(0x00000100, &axi_qos->qosconf);
967 writel(0x00002042, &axi_qos->qosctset0);
968 writel(0x00000001, &axi_qos->qosreqctr);
969 writel(0x00002050, &axi_qos->qosthres0);
970 writel(0x00002032, &axi_qos->qosthres1);
971 writel(0x00002014, &axi_qos->qosthres2);
972 writel(0x00000001, &axi_qos->qosqon);
973
974 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
975 writel(0x00000100, &axi_qos->qosconf);
976 writel(0x0000204C, &axi_qos->qosctset0);
977 writel(0x00000001, &axi_qos->qosreqctr);
978 writel(0x00002050, &axi_qos->qosthres0);
979 writel(0x00002032, &axi_qos->qosthres1);
980 writel(0x00002014, &axi_qos->qosthres2);
981 writel(0x00000001, &axi_qos->qosqon);
982
983 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
984 writel(0x00000100, &axi_qos->qosconf);
985 writel(0x00002200, &axi_qos->qosctset0);
986 writel(0x00000001, &axi_qos->qosreqctr);
987 writel(0x00002050, &axi_qos->qosthres0);
988 writel(0x00002032, &axi_qos->qosthres1);
989 writel(0x00002014, &axi_qos->qosthres2);
990 writel(0x00000001, &axi_qos->qosqon);
991
992 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
993 writel(0x00000100, &axi_qos->qosconf);
994 writel(0x00002455, &axi_qos->qosctset0);
995 writel(0x00000001, &axi_qos->qosreqctr);
996 writel(0x00002050, &axi_qos->qosthres0);
997 writel(0x00002032, &axi_qos->qosthres1);
998 writel(0x00002014, &axi_qos->qosthres2);
999 writel(0x00000001, &axi_qos->qosqon);
1000
1001 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
1002 writel(0x00000100, &axi_qos->qosconf);
1003 writel(0x00002455, &axi_qos->qosctset0);
1004 writel(0x00000001, &axi_qos->qosreqctr);
1005 writel(0x00002050, &axi_qos->qosthres0);
1006 writel(0x00002032, &axi_qos->qosthres1);
1007 writel(0x00002014, &axi_qos->qosthres2);
1008 writel(0x00000001, &axi_qos->qosqon);
1009
1010 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
1011 writel(0x00000100, &axi_qos->qosconf);
1012 writel(0x0000204C, &axi_qos->qosctset0);
1013 writel(0x00000001, &axi_qos->qosreqctr);
1014 writel(0x00002050, &axi_qos->qosthres0);
1015 writel(0x00002032, &axi_qos->qosthres1);
1016 writel(0x00002014, &axi_qos->qosthres2);
1017 writel(0x00000001, &axi_qos->qosqon);
1018
1019 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
1020 writel(0x00000100, &axi_qos->qosconf);
1021 writel(0x00002200, &axi_qos->qosctset0);
1022 writel(0x00000001, &axi_qos->qosreqctr);
1023 writel(0x00002050, &axi_qos->qosthres0);
1024 writel(0x00002032, &axi_qos->qosthres1);
1025 writel(0x00002014, &axi_qos->qosthres2);
1026 writel(0x00000001, &axi_qos->qosqon);
1027
1028 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
1029 writel(0x00000100, &axi_qos->qosconf);
1030 writel(0x00002455, &axi_qos->qosctset0);
1031 writel(0x00000001, &axi_qos->qosreqctr);
1032 writel(0x00002050, &axi_qos->qosthres0);
1033 writel(0x00002032, &axi_qos->qosthres1);
1034 writel(0x00002014, &axi_qos->qosthres2);
1035 writel(0x00000001, &axi_qos->qosqon);
1036
1037 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
1038 writel(0x00000100, &axi_qos->qosconf);
1039 writel(0x00002455, &axi_qos->qosctset0);
1040 writel(0x00000001, &axi_qos->qosreqctr);
1041 writel(0x00002050, &axi_qos->qosthres0);
1042 writel(0x00002032, &axi_qos->qosthres1);
1043 writel(0x00002014, &axi_qos->qosthres2);
1044 writel(0x00000001, &axi_qos->qosqon);
1045
1046 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
1047 writel(0x00000100, &axi_qos->qosconf);
1048 writel(0x0000204C, &axi_qos->qosctset0);
1049 writel(0x00000001, &axi_qos->qosreqctr);
1050 writel(0x00002050, &axi_qos->qosthres0);
1051 writel(0x00002032, &axi_qos->qosthres1);
1052 writel(0x00002014, &axi_qos->qosthres2);
1053 writel(0x00000001, &axi_qos->qosqon);
1054
1055 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
1056 writel(0x00000100, &axi_qos->qosconf);
1057 writel(0x00002200, &axi_qos->qosctset0);
1058 writel(0x00000001, &axi_qos->qosreqctr);
1059 writel(0x00002050, &axi_qos->qosthres0);
1060 writel(0x00002032, &axi_qos->qosthres1);
1061 writel(0x00002014, &axi_qos->qosthres2);
1062 writel(0x00000001, &axi_qos->qosqon);
1063
1064 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
1065 writel(0x00000100, &axi_qos->qosconf);
1066 writel(0x00002455, &axi_qos->qosctset0);
1067 writel(0x00000001, &axi_qos->qosreqctr);
1068 writel(0x00002050, &axi_qos->qosthres0);
1069 writel(0x00002032, &axi_qos->qosthres1);
1070 writel(0x00002014, &axi_qos->qosthres2);
1071 writel(0x00000001, &axi_qos->qosqon);
1072
1073 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
1074 writel(0x00000100, &axi_qos->qosconf);
1075 writel(0x00002455, &axi_qos->qosctset0);
1076 writel(0x00000001, &axi_qos->qosreqctr);
1077 writel(0x00002050, &axi_qos->qosthres0);
1078 writel(0x00002032, &axi_qos->qosthres1);
1079 writel(0x00002014, &axi_qos->qosthres2);
1080 writel(0x00000001, &axi_qos->qosqon);
1081
1082 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
1083 writel(0x00000100, &axi_qos->qosconf);
1084 writel(0x0000204C, &axi_qos->qosctset0);
1085 writel(0x00000001, &axi_qos->qosreqctr);
1086 writel(0x00002050, &axi_qos->qosthres0);
1087 writel(0x00002032, &axi_qos->qosthres1);
1088 writel(0x00002014, &axi_qos->qosthres2);
1089 writel(0x00000001, &axi_qos->qosqon);
1090
1091 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
1092 writel(0x00000100, &axi_qos->qosconf);
1093 writel(0x00002200, &axi_qos->qosctset0);
1094 writel(0x00000001, &axi_qos->qosreqctr);
1095 writel(0x00002050, &axi_qos->qosthres0);
1096 writel(0x00002032, &axi_qos->qosthres1);
1097 writel(0x00002014, &axi_qos->qosthres2);
1098 writel(0x00000001, &axi_qos->qosqon);
1099
1100 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
1101 writel(0x00000100, &axi_qos->qosconf);
1102 writel(0x00002455, &axi_qos->qosctset0);
1103 writel(0x00000001, &axi_qos->qosreqctr);
1104 writel(0x00002050, &axi_qos->qosthres0);
1105 writel(0x00002032, &axi_qos->qosthres1);
1106 writel(0x00002014, &axi_qos->qosthres2);
1107 writel(0x00000001, &axi_qos->qosqon);
1108
1109 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
1110 writel(0x00000100, &axi_qos->qosconf);
1111 writel(0x00002455, &axi_qos->qosctset0);
1112 writel(0x00000001, &axi_qos->qosreqctr);
1113 writel(0x00002050, &axi_qos->qosthres0);
1114 writel(0x00002032, &axi_qos->qosthres1);
1115 writel(0x00002014, &axi_qos->qosthres2);
1116 writel(0x00000001, &axi_qos->qosqon);
1117
1118 /* DMS Register(SYS-AXI) */
1119 writel(0x00000000, SYS_AXI_AVBDMSCR);
1120 writel(0x00000000, SYS_AXI_AX2MDMSCR);
1121 writel(0x00000000, SYS_AXI_CC50DMSCR);
1122 writel(0x00000000, SYS_AXI_CCIDMSCR);
1123 writel(0x00000000, SYS_AXI_CSDMSCR);
1124 writel(0x00000000, SYS_AXI_G2DDMSCR);
1125 writel(0x00000000, SYS_AXI_IMP1DMSCR);
1126 writel(0x00000000, SYS_AXI_LBSMDMSCR);
1127 writel(0x00000000, SYS_AXI_MMUDSDMSCR);
1128 writel(0x00000000, SYS_AXI_MMUMXDMSCR);
1129 writel(0x00000000, SYS_AXI_MMUS0DMSCR);
1130 writel(0x00000000, SYS_AXI_MMUS1DMSCR);
1131 writel(0x00000000, SYS_AXI_RTMXDMSCR);
1132 writel(0x00000000, SYS_AXI_SDM0DMSCR);
1133 writel(0x00000000, SYS_AXI_SDM1DMSCR);
1134 writel(0x00000000, SYS_AXI_SDS0DMSCR);
1135 writel(0x00000000, SYS_AXI_SDS1DMSCR);
1136 writel(0x00000000, SYS_AXI_TRABDMSCR);
1137 writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
1138 writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
1139 writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
1140 writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
1141 writel(0x00000000, SYS_AXI_GICSLVDMSCR);
1142 writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
1143 writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
1144 writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
1145 writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
1146 writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
1147 writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
1148 writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
1149 writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
1150 writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
1151 writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
1152 writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
1153 writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
1154 writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
1155 writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
1156 writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
1157 writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
1158 writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
1159 writel(0x00000000, SYS_AXI_STBSLVDMSCR);
1160 writel(0x00000000, SYS_AXI_STMSLVDMSCR);
1161 writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
1162 writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
1163 writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
1164 writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
1165 writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
1166 writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
1167 writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
1168 writel(0x00000000, SYS_AXI_ROT0DMSCR);
1169 writel(0x00000000, SYS_AXI_ROT1DMSCR);
1170 writel(0x00000000, SYS_AXI_ROT2DMSCR);
1171 writel(0x00000000, SYS_AXI_ROT3DMSCR);
1172 writel(0x00000000, SYS_AXI_ROT4DMSCR);
1173 writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
1174 writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
1175 writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
1176 writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
1177 writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
1178 writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
1179 writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
1180 writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
1181 writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
1182 writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
1183 writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
1184 writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
1185 writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
1186 writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
1187 writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
1188 writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
1189 writel(0x00000000, SYS_AXI_ADM_DMSCR);
1190 writel(0x00000000, SYS_AXI_ADS_DMSCR);
1191
1192 /* DMS Register(RT-AXI) */
1193 writel(0x00000000, DM_AXI_DMAXICONF);
1194 writel(0x00000019, DM_AXI_DMAPBCONF);
1195 writel(0x00000000, DM_AXI_DMADMCONF);
1196 writel(0x00000000, DM_AXI_DMSDM0CONF);
1197 writel(0x00000000, DM_AXI_DMSDM1CONF);
1198 writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
1199 writel(0x00000004, DM_AXI_RAPD4SLVCONF);
1200 writel(0x00000004, DM_AXI_SAPD4SLVCONF);
1201 writel(0x00000004, DM_AXI_SAPD5SLVCONF);
1202 writel(0x00000004, DM_AXI_SAPD6SLVCONF);
1203 writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
1204 writel(0x00000004, DM_AXI_SDAP0SLVCONF);
1205 writel(0x00000004, DM_AXI_MAPD2SLVCONF);
1206 writel(0x00000004, DM_AXI_MAPD3SLVCONF);
1207 writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
1208 writel(0x00000100, DM_AXI_DMADMRQOSCONF);
1209 writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
1210 writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
1211 writel(0x00000001, DM_AXI_DMADMRQOSQON);
1212 writel(0x00000005, DM_AXI_DMADMRQOSIN);
1213 writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
1214 writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
1215 writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
1216 writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
1217 writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
1218 writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
1219 writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
1220 writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
1221 writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
1222 writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
1223 writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
1224 writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
1225 writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
1226 writel(0x00002041, DM_AXI_DMRQOSCTSET1);
1227 writel(0x00002023, DM_AXI_DMRQOSCTSET2);
1228 writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
1229 writel(0x00002050, DM_AXI_DMRQOSTHRES0);
1230 writel(0x00002032, DM_AXI_DMRQOSTHRES1);
1231 writel(0x00002014, DM_AXI_DMRQOSTHRES2);
1232 writel(0x00000100, DM_AXI_DMADMWQOSCONF);
1233 writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
1234 writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
1235 writel(0x00000001, DM_AXI_DMADMWQOSQON);
1236 writel(0x00000005, DM_AXI_DMADMWQOSIN);
1237 writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
1238 writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
1239 writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
1240 writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
1241 writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
1242 writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
1243 writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
1244 writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
1245 writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
1246 writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
1247 writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
1248 writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
1249 writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
1250 writel(0x00002041, DM_AXI_DMWQOSCTSET1);
1251 writel(0x00002023, DM_AXI_DMWQOSCTSET2);
1252 writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
1253 writel(0x00002050, DM_AXI_DMWQOSTHRES0);
1254 writel(0x00002032, DM_AXI_DMWQOSTHRES1);
1255 writel(0x00002014, DM_AXI_DMWQOSTHRES2);
1256 writel(0x00000000, DM_AXI_RDMDMSCR);
1257 writel(0x00000000, DM_AXI_SDM0DMSCR);
1258 writel(0x00000000, DM_AXI_SDM1DMSCR);
1259 writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
1260 writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
1261 writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
1262 writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
1263 writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
1264 writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
1265 writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
1266 writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
1267 writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
1268 writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
1269 writel(0x00000001, DM_AXI_DMXREGDMSENN);
1270
1271 /* DMS Register(SYS-AXI256) */
1272 writel(0x00000000, SYS_AXI256_SYXDMSCR);
1273 writel(0x00000000, SYS_AXI256_MXIDMSCR);
1274 writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
1275 writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
1276 writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
1277 writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
1278 writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
1279
1280 /* DMS Register(MXT) */
1281 writel(0x00000000, MXT_SYXDMSCR);
1282 writel(0x00000000, MXT_IMRSLVDMSCR);
1283 writel(0x00000000, MXT_VINSLVDMSCR);
1284 writel(0x00000000, MXT_VPC1SLVDMSCR);
1285 writel(0x00000000, MXT_VSPD0SLVDMSCR);
1286 writel(0x00000000, MXT_VSPD1SLVDMSCR);
1287 writel(0x00000000, MXT_MAP1SLVDMSCR);
1288 writel(0x00000000, MXT_MAP2SLVDMSCR);
1289 writel(0x00000000, MXT_MAP2BSLVDMSCR);
1290
1291 /* DMS Register(MXI) */
1292 writel(0x00000002, MXI_JPURDMSCR);
1293 writel(0x00000002, MXI_JPUWDMSCR);
1294 writel(0x00000002, MXI_VCTU0RDMSCR);
1295 writel(0x00000002, MXI_VCTU0WDMSCR);
1296 writel(0x00000002, MXI_VDCTU0RDMSCR);
1297 writel(0x00000002, MXI_VDCTU0WDMSCR);
1298 writel(0x00000002, MXI_VDCTU1RDMSCR);
1299 writel(0x00000002, MXI_VDCTU1WDMSCR);
1300 writel(0x00000002, MXI_VIN0WDMSCR);
1301 writel(0x00000002, MXI_VIN1WDMSCR);
1302 writel(0x00000002, MXI_RDRWDMSCR);
1303 writel(0x00000002, MXI_IMS01RDMSCR);
1304 writel(0x00000002, MXI_IMS01WDMSCR);
1305 writel(0x00000002, MXI_IMS23RDMSCR);
1306 writel(0x00000002, MXI_IMS23WDMSCR);
1307 writel(0x00000002, MXI_IMS45RDMSCR);
1308 writel(0x00000002, MXI_IMS45WDMSCR);
1309 writel(0x00000002, MXI_IMRRDMSCR);
1310 writel(0x00000002, MXI_IMRWDMSCR);
1311 writel(0x00000002, MXI_ROTCE4RDMSCR);
1312 writel(0x00000002, MXI_ROTCE4WDMSCR);
1313 writel(0x00000002, MXI_ROTVLC4RDMSCR);
1314 writel(0x00000002, MXI_ROTVLC4WDMSCR);
1315 writel(0x00000002, MXI_VSPD0RDMSCR);
1316 writel(0x00000002, MXI_VSPD0WDMSCR);
1317 writel(0x00000002, MXI_VSPD1RDMSCR);
1318 writel(0x00000002, MXI_VSPD1WDMSCR);
1319 writel(0x00000002, MXI_DU0RDMSCR);
1320 writel(0x00000002, MXI_DU0WDMSCR);
1321 writel(0x00000002, MXI_VSP0RDMSCR);
1322 writel(0x00000002, MXI_VSP0WDMSCR);
1323 writel(0x00000002, MXI_ROTCE0RDMSCR);
1324 writel(0x00000002, MXI_ROTCE0WDMSCR);
1325 writel(0x00000002, MXI_ROTVLC0RDMSCR);
1326 writel(0x00000002, MXI_ROTVLC0WDMSCR);
1327 writel(0x00000002, MXI_ROTCE1RDMSCR);
1328 writel(0x00000002, MXI_ROTCE1WDMSCR);
1329 writel(0x00000002, MXI_ROTVLC1RDMSCR);
1330 writel(0x00000002, MXI_ROTVLC1WDMSCR);
1331 writel(0x00000002, MXI_ROTCE2RDMSCR);
1332 writel(0x00000002, MXI_ROTCE2WDMSCR);
1333 writel(0x00000002, MXI_ROTVLC2RDMSCR);
1334 writel(0x00000002, MXI_ROTVLC2WDMSCR);
1335 writel(0x00000002, MXI_ROTCE3RDMSCR);
1336 writel(0x00000002, MXI_ROTCE3WDMSCR);
1337 writel(0x00000002, MXI_ROTVLC3RDMSCR);
1338 writel(0x00000002, MXI_ROTVLC3WDMSCR);
1339
1340 /* DMS Register(CCI-AXI) */
1341 writel(0x00000000, CCI_AXI_MMUS0DMSCR);
1342 writel(0x00000000, CCI_AXI_SYX2DMSCR);
1343 writel(0x00000000, CCI_AXI_MMURDMSCR);
1344 writel(0x00000000, CCI_AXI_MMUDSDMSCR);
1345 writel(0x00000000, CCI_AXI_MMUMDMSCR);
1346 writel(0x00000000, CCI_AXI_MXIDMSCR);
1347 writel(0x00000000, CCI_AXI_MMUS1DMSCR);
1348 writel(0x00000000, CCI_AXI_MMUMPDMSCR);
1349 writel(0x00000000, CCI_AXI_DVMDMSCR);
1350 writel(0x00000000, CCI_AXI_CCISLVDMSCR);
1351
1352 /* CC-AXI Function Register */
1353 writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
1354 writel(0x00000011, CCI_AXI_IPMMURDVMCR);
1355 writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
1356 writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
1357 writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
1358 writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
1359 writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
1360
1361}
1362#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
1363void qos_init(void)
1364{
1365}
1366#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */