Keerthy | f0df1b1 | 2016-09-30 09:20:43 +0530 | [diff] [blame] | 1 | #define PALMAS 0x0 |
| 2 | #define TPS659038 0x1 |
| 3 | #define TPS65917 0x2 |
| 4 | |
Svyatoslav Ryhel | eacea67 | 2023-10-24 10:49:08 +0300 | [diff] [blame] | 5 | struct palmas_priv { |
| 6 | struct udevice *chip2; |
| 7 | }; |
| 8 | |
Keerthy | f0df1b1 | 2016-09-30 09:20:43 +0530 | [diff] [blame] | 9 | /* I2C device address for pmic palmas */ |
| 10 | #define PALMAS_I2C_ADDR (0x12 >> 1) |
| 11 | #define PALMAS_LDO_NUM 11 |
| 12 | #define PALMAS_SMPS_NUM 8 |
| 13 | |
| 14 | /* Drivers name */ |
| 15 | #define PALMAS_LDO_DRIVER "palmas_ldo" |
| 16 | #define PALMAS_SMPS_DRIVER "palmas_smps" |
Svyatoslav Ryhel | eacea67 | 2023-10-24 10:49:08 +0300 | [diff] [blame] | 17 | #define PALMAS_RST_DRIVER "palmas_rst" |
Svyatoslav Ryhel | 32648d3 | 2023-07-21 10:50:15 +0300 | [diff] [blame] | 18 | #define PALMAS_GPIO_DRIVER "palmas_gpio" |
Keerthy | f0df1b1 | 2016-09-30 09:20:43 +0530 | [diff] [blame] | 19 | |
| 20 | #define PALMAS_SMPS_VOLT_MASK 0x7F |
| 21 | #define PALMAS_SMPS_RANGE_MASK 0x80 |
| 22 | #define PALMAS_SMPS_VOLT_MAX_HEX 0x7F |
| 23 | #define PALMAS_SMPS_VOLT_MAX 3300000 |
| 24 | #define PALMAS_SMPS_MODE_MASK 0x3 |
| 25 | #define PALMAS_SMPS_STATUS_MASK 0x30 |
| 26 | |
| 27 | #define PALMAS_LDO_VOLT_MASK 0x3F |
| 28 | #define PALMAS_LDO_VOLT_MAX_HEX 0x3F |
| 29 | #define PALMAS_LDO_VOLT_MAX 3300000 |
| 30 | #define PALMAS_LDO_MODE_MASK 0x1 |
| 31 | #define PALMAS_LDO_STATUS_MASK 0x10 |
Jean-Jacques Hiblot | 9182741 | 2017-07-12 11:42:47 +0200 | [diff] [blame] | 32 | #define PALMAS_LDO_BYPASS_EN 0x40 |
Svyatoslav Ryhel | eacea67 | 2023-10-24 10:49:08 +0300 | [diff] [blame] | 33 | |
| 34 | #define PALMAS_DEV_CTRL 0xA0 |
| 35 | #define SW_RST BIT(1) |
| 36 | #define DEV_OFF 0x00 |
| 37 | #define PALMAS_INT3_MASK 0x1B |
| 38 | #define MASK_VBUS BIT(7) |
Svyatoslav Ryhel | 32648d3 | 2023-07-21 10:50:15 +0300 | [diff] [blame] | 39 | |
| 40 | /* second chip */ |
| 41 | #define PALMAS_GPIO_DATA_IN 0x80 |
| 42 | #define PALMAS_GPIO_DATA_DIR 0x81 |
| 43 | #define PALMAS_GPIO_DATA_OUT 0x82 |
| 44 | #define PALMAS_GPIO_DEBOUNCE_EN 0x83 |
| 45 | #define PALMAS_GPIO_CLEAR_DATA_OUT 0x84 |
| 46 | #define PALMAS_GPIO_SET_DATA_OUT 0x85 |
| 47 | #define PALMAS_PU_PD_GPIO_CTRL1 0x86 |
| 48 | #define PALMAS_PU_PD_GPIO_CTRL2 0x87 |
| 49 | #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88 |