| Jagan Teki | 5a03d1d | 2023-01-30 20:27:41 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2021 Rockchip Electronics Co., Ltd. |
| 4 | */ |
| 5 | #ifndef _ASM_ARCH_IOC_RK3588_H |
| 6 | #define _ASM_ARCH_IOC_RK3588_H |
| 7 | |
| 8 | struct rk3588_bus_ioc { |
| 9 | unsigned int reserved0000[3]; /* Address Offset: 0x0000 */ |
| 10 | unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ |
| 11 | unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */ |
| 12 | unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */ |
| 13 | unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */ |
| 14 | unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x001C */ |
| 15 | unsigned int gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ |
| 16 | unsigned int gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ |
| 17 | unsigned int gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ |
| 18 | unsigned int gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ |
| 19 | unsigned int gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ |
| 20 | unsigned int gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ |
| 21 | unsigned int gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ |
| 22 | unsigned int gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ |
| 23 | unsigned int gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ |
| 24 | unsigned int gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ |
| 25 | unsigned int gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */ |
| 26 | unsigned int gpio2b_iomux_sel_h; /* Address Offset: 0x004C */ |
| 27 | unsigned int gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */ |
| 28 | unsigned int gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */ |
| 29 | unsigned int gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */ |
| 30 | unsigned int gpio2d_iomux_sel_h; /* Address Offset: 0x005C */ |
| 31 | unsigned int gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ |
| 32 | unsigned int gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ |
| 33 | unsigned int gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ |
| 34 | unsigned int gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ |
| 35 | unsigned int gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ |
| 36 | unsigned int gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */ |
| 37 | unsigned int gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */ |
| 38 | unsigned int gpio3d_iomux_sel_h; /* Address Offset: 0x007C */ |
| 39 | unsigned int gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ |
| 40 | unsigned int gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ |
| 41 | unsigned int gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ |
| 42 | unsigned int gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ |
| 43 | unsigned int gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ |
| 44 | unsigned int gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ |
| 45 | unsigned int gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ |
| 46 | unsigned int gpio4d_iomux_sel_h; /* Address Offset: 0x009C */ |
| 47 | }; |
| 48 | |
| 49 | check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); |
| 50 | |
| 51 | struct rk3588_pmu1_ioc { |
| 52 | unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ |
| 53 | unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ |
| 54 | unsigned int gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */ |
| 55 | unsigned int reserved0012; /* Address Offset: 0x000C */ |
| 56 | unsigned int gpio0a_ds_l; /* Address Offset: 0x0010 */ |
| 57 | unsigned int gpio0a_ds_h; /* Address Offset: 0x0014 */ |
| 58 | unsigned int gpio0b_ds_l; /* Address Offset: 0x0018 */ |
| 59 | unsigned int reserved0028; /* Address Offset: 0x001C */ |
| 60 | unsigned int gpio0a_p; /* Address Offset: 0x0020 */ |
| 61 | unsigned int gpio0b_p; /* Address Offset: 0x0024 */ |
| 62 | unsigned int gpio0a_ie; /* Address Offset: 0x0028 */ |
| 63 | unsigned int gpio0b_ie; /* Address Offset: 0x002C */ |
| 64 | unsigned int gpio0a_smt; /* Address Offset: 0x0030 */ |
| 65 | unsigned int gpio0b_smt; /* Address Offset: 0x0034 */ |
| 66 | unsigned int gpio0a_pdis; /* Address Offset: 0x0038 */ |
| 67 | unsigned int gpio0b_pdis; /* Address Offset: 0x003C */ |
| 68 | unsigned int xin_con; /* Address Offset: 0x0040 */ |
| 69 | }; |
| 70 | |
| 71 | check_member(rk3588_pmu1_ioc, xin_con, 0x0040); |
| 72 | |
| 73 | struct rk3588_pmu2_ioc { |
| 74 | unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ |
| 75 | unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ |
| 76 | unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */ |
| 77 | unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x000C */ |
| 78 | unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */ |
| 79 | unsigned int gpio0b_ds_h; /* Address Offset: 0x0014 */ |
| 80 | unsigned int gpio0c_ds_l; /* Address Offset: 0x0018 */ |
| 81 | unsigned int gpio0c_ds_h; /* Address Offset: 0x001C */ |
| 82 | unsigned int gpio0d_ds_l; /* Address Offset: 0x0020 */ |
| 83 | unsigned int gpio0d_ds_h; /* Address Offset: 0x0024 */ |
| 84 | unsigned int gpio0b_p; /* Address Offset: 0x0028 */ |
| 85 | unsigned int gpio0c_p; /* Address Offset: 0x002C */ |
| 86 | unsigned int gpio0d_p; /* Address Offset: 0x0030 */ |
| 87 | unsigned int gpio0b_ie; /* Address Offset: 0x0034 */ |
| 88 | unsigned int gpio0c_ie; /* Address Offset: 0x0038 */ |
| 89 | unsigned int gpio0d_ie; /* Address Offset: 0x003C */ |
| 90 | unsigned int gpio0b_smt; /* Address Offset: 0x0040 */ |
| 91 | unsigned int gpio0c_smt; /* Address Offset: 0x0044 */ |
| 92 | unsigned int gpio0d_smt; /* Address Offset: 0x0048 */ |
| 93 | unsigned int gpio0b_pdis; /* Address Offset: 0x004C */ |
| 94 | unsigned int gpio0c_pdis; /* Address Offset: 0x0050 */ |
| 95 | unsigned int gpio0d_pdis; /* Address Offset: 0x0054 */ |
| 96 | }; |
| 97 | |
| 98 | check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054); |
| 99 | |
| 100 | #endif |
| 101 | |