wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Martin Winistoerfer, martinwinistoerfer@gmx.ch. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 20 | * Foundation, |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * File: 5xx_immap.h |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 25 | * |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 26 | * Discription: MPC555 Internal Memory Map |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 27 | * |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 28 | */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 29 | |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 30 | #ifndef __IMMAP_5XX__ |
| 31 | #define __IMMAP_5XX__ |
| 32 | |
| 33 | /* System Configuration Registers. |
| 34 | */ |
| 35 | typedef struct sys_conf { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 36 | uint sc_siumcr; |
| 37 | uint sc_sypcr; |
| 38 | char res1[6]; |
| 39 | ushort sc_swsr; |
| 40 | uint sc_sipend; |
| 41 | uint sc_simask; |
| 42 | uint sc_siel; |
| 43 | uint sc_sivec; |
| 44 | uint sc_tesr; |
| 45 | uint sc_sgpiodt1; |
| 46 | uint sc_sgpiodt2; |
| 47 | uint sc_sgpiocr; |
| 48 | uint sc_emcr; |
| 49 | uint sc_res1aa; |
| 50 | uint sc_res1ab; |
| 51 | uint sc_pdmcr; |
| 52 | char res3[192]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 53 | } sysconf5xx_t; |
| 54 | |
| 55 | |
| 56 | /* Memory Controller Registers. |
| 57 | */ |
| 58 | typedef struct mem_ctlr { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 59 | uint memc_br0; |
| 60 | uint memc_or0; |
| 61 | uint memc_br1; |
| 62 | uint memc_or1; |
| 63 | uint memc_br2; |
| 64 | uint memc_or2; |
| 65 | uint memc_br3; |
| 66 | uint memc_or3; |
| 67 | char res1[32]; |
| 68 | uint memc_dmbr; |
| 69 | uint memc_dmor; |
| 70 | char res2[48]; |
| 71 | ushort memc_mstat; |
| 72 | ushort memc_res4a; |
| 73 | char res3[132]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 74 | } memctl5xx_t; |
| 75 | |
| 76 | /* System Integration Timers. |
| 77 | */ |
| 78 | typedef struct sys_int_timers { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 79 | ushort sit_tbscr; |
| 80 | char res1[2]; |
| 81 | uint sit_tbref0; |
| 82 | uint sit_tbref1; |
| 83 | char res2[20]; |
| 84 | ushort sit_rtcsc; |
| 85 | char res3[2]; |
| 86 | uint sit_rtc; |
| 87 | uint sit_rtsec; |
| 88 | uint sit_rtcal; |
| 89 | char res4[16]; |
| 90 | ushort sit_piscr; |
| 91 | char res5[2]; |
| 92 | uint sit_pitc; |
| 93 | uint sit_pitr; |
| 94 | char res6[52]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 95 | } sit5xx_t; |
| 96 | |
| 97 | /* Clocks and Reset |
| 98 | */ |
| 99 | typedef struct clk_and_reset { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 100 | uint car_sccr; |
| 101 | uint car_plprcr; |
| 102 | ushort car_rsr; |
| 103 | ushort car_res7a; |
| 104 | ushort car_colir; |
| 105 | ushort car_res7b; |
| 106 | ushort car_vsrmcr; |
| 107 | ushort car_res7c; |
| 108 | char res1[108]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 109 | |
| 110 | } car5xx_t; |
| 111 | |
| 112 | #define TBSCR_TBE ((ushort)0x0001) |
| 113 | |
| 114 | /* System Integration Timer Keys |
| 115 | */ |
| 116 | typedef struct sitk { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 117 | uint sitk_tbscrk; |
| 118 | uint sitk_tbref0k; |
| 119 | uint sitk_tbref1k; |
| 120 | uint sitk_tbk; |
| 121 | char res1[16]; |
| 122 | uint sitk_rtcsck; |
| 123 | uint sitk_rtck; |
| 124 | uint sitk_rtseck; |
| 125 | uint sitk_rtcalk; |
| 126 | char res2[16]; |
| 127 | uint sitk_piscrk; |
| 128 | uint sitk_pitck; |
| 129 | char res3[56]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 130 | } sitk5xx_t; |
| 131 | |
| 132 | /* Clocks and Reset Keys. |
| 133 | */ |
| 134 | typedef struct cark { |
| 135 | uint cark_sccrk; |
| 136 | uint cark_plprcrk; |
| 137 | uint cark_rsrk; |
| 138 | char res1[1140]; |
| 139 | } cark8xx_t; |
| 140 | |
| 141 | /* The key to unlock registers maintained by keep-alive power. |
| 142 | */ |
| 143 | #define KAPWR_KEY ((unsigned int)0x55ccaa33) |
| 144 | |
| 145 | /* Flash Configuration |
| 146 | */ |
| 147 | typedef struct fl { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 148 | uint fl_cmfmcr; |
| 149 | uint fl_cmftst; |
| 150 | uint fl_cmfctl; |
| 151 | char res1[52]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 152 | } fl5xx_t; |
| 153 | |
| 154 | /* Dpram Control |
| 155 | */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 156 | typedef struct dprc { |
| 157 | ushort dprc_dptmcr; |
| 158 | ushort dprc_ramtst; |
| 159 | ushort dprc_rambar; |
| 160 | ushort dprc_misrh; |
| 161 | ushort dprc_misrl; |
| 162 | ushort dprc_miscnt; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 163 | } dprc5xx_t; |
| 164 | |
| 165 | /* Time Processor Unit |
| 166 | */ |
| 167 | typedef struct tpu { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 168 | ushort tpu_tpumcr; |
| 169 | ushort tpu_tcr; |
| 170 | ushort tpu_dscr; |
| 171 | ushort tpu_dssr; |
| 172 | ushort tpu_ticr; |
| 173 | ushort tpu_cier; |
| 174 | ushort tpu_cfsr0; |
| 175 | ushort tpu_cfsr1; |
| 176 | ushort tpu_cfsr2; |
| 177 | ushort tpu_cfsr3; |
| 178 | ushort tpu_hsqr0; |
| 179 | ushort tpu_hsqr1; |
| 180 | ushort tpu_hsrr0; |
| 181 | ushort tpu_hsrr1; |
| 182 | ushort tpu_cpr0; |
| 183 | ushort tpu_cpr1; |
| 184 | ushort tpu_cisr; |
| 185 | ushort tpu_lr; |
| 186 | ushort tpu_sglr; |
| 187 | ushort tpu_dcnr; |
| 188 | ushort tpu_tpumcr2; |
| 189 | ushort tpu_tpumcr3; |
| 190 | ushort tpu_isdr; |
| 191 | ushort tpu_iscr; |
| 192 | char res1[208]; |
| 193 | char tpu[16][16]; |
| 194 | char res2[512]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 195 | } tpu5xx_t; |
| 196 | |
| 197 | /* QADC |
| 198 | */ |
| 199 | typedef struct qadc { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 200 | ushort qadc_64mcr; |
| 201 | ushort qadc_64test; |
| 202 | ushort qadc_64int; |
| 203 | u_char qadc_portqa; |
| 204 | u_char qadc_portqb; |
| 205 | ushort qadc_ddrqa; |
| 206 | ushort qadc_qacr0; |
| 207 | ushort qadc_qacr1; |
| 208 | ushort qadc_qacr2; |
| 209 | ushort qadc_qasr0; |
| 210 | ushort qadc_qasr1; |
| 211 | char res1[492]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 212 | /* command convertion word table */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 213 | ushort qadc_ccw[64]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 214 | /* result word table, unsigned right justified */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 215 | ushort qadc_rjurr[64]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 216 | /* result word table, signed left justified */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 217 | ushort qadc_ljsrr[64]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 218 | /* result word table, unsigned left justified */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 219 | ushort qadc_ljurr[64]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 220 | } qadc5xx_t; |
| 221 | |
| 222 | /* QSMCM |
| 223 | */ |
| 224 | typedef struct qsmcm { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 225 | ushort qsmcm_qsmcr; |
| 226 | ushort qsmcm_qtest; |
| 227 | ushort qsmcm_qdsci_il; |
| 228 | ushort qsmcm_qspi_il; |
| 229 | ushort qsmcm_scc1r0; |
| 230 | ushort qsmcm_scc1r1; |
| 231 | ushort qsmcm_sc1sr; |
| 232 | ushort qsmcm_sc1dr; |
| 233 | char res1[2]; |
| 234 | char res2[2]; |
| 235 | ushort qsmcm_portqs; |
| 236 | u_char qsmcm_pqspar; |
| 237 | u_char qsmcm_ddrqs; |
| 238 | ushort qsmcm_spcr0; |
| 239 | ushort qsmcm_spcr1; |
| 240 | ushort qsmcm_spcr2; |
| 241 | u_char qsmcm_spcr3; |
| 242 | u_char qsmcm_spsr; |
| 243 | ushort qsmcm_scc2r0; |
| 244 | ushort qsmcm_scc2r1; |
| 245 | ushort qsmcm_sc2sr; |
| 246 | ushort qsmcm_sc2dr; |
| 247 | ushort qsmcm_qsci1cr; |
| 248 | ushort qsmcm_qsci1sr; |
| 249 | ushort qsmcm_sctq[16]; |
| 250 | ushort qsmcm_scrq[16]; |
| 251 | char res3[212]; |
| 252 | ushort qsmcm_recram[32]; |
| 253 | ushort qsmcm_tranram[32]; |
| 254 | u_char qsmcm_comdram[32]; |
| 255 | char res[3616]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 256 | } qsmcm5xx_t; |
| 257 | |
| 258 | |
| 259 | /* MIOS |
| 260 | */ |
| 261 | |
| 262 | typedef struct mios { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 263 | ushort mios_mpwmsm0perr; /* mpwmsm0 */ |
| 264 | ushort mios_mpwmsm0pulr; |
| 265 | ushort mios_mpwmsm0cntr; |
| 266 | ushort mios_mpwmsm0scr; |
| 267 | ushort mios_mpwmsm1perr; /* mpwmsm1 */ |
| 268 | ushort mios_mpwmsm1pulr; |
| 269 | ushort mios_mpwmsm1cntr; |
| 270 | ushort mios_mpwmsm1scr; |
| 271 | ushort mios_mpwmsm2perr; /* mpwmsm2 */ |
| 272 | ushort mios_mpwmsm2pulr; |
| 273 | ushort mios_mpwmsm2cntr; |
| 274 | ushort mios_mpwmsm2scr; |
| 275 | ushort mios_mpwmsm3perr; /* mpwmsm3 */ |
| 276 | ushort mios_mpwmsm3pulr; |
| 277 | ushort mios_mpwmsm3cntr; |
| 278 | ushort mios_mpwmsm3scr; |
| 279 | char res1[16]; |
| 280 | ushort mios_mmcsm6cnt; /* mmcsm6 */ |
| 281 | ushort mios_mmcsm6mlr; |
| 282 | ushort mios_mmcsm6scrd, mmcsm6scr; |
| 283 | char res2[32]; |
| 284 | ushort mios_mdasm11ar; /* mdasm11 */ |
| 285 | ushort mios_mdasm11br; |
| 286 | ushort mios_mdasm11scrd, mdasm11scr; |
| 287 | ushort mios_mdasm12ar; /* mdasm12 */ |
| 288 | ushort mios_mdasm12br; |
| 289 | ushort mios_mdasm12scrd, mdasm12scr; |
| 290 | ushort mios_mdasm13ar; /* mdasm13 */ |
| 291 | ushort mios_mdasm13br; |
| 292 | ushort mios_mdasm13scrd, mdasm13scr; |
| 293 | ushort mios_mdasm14ar; /* mdasm14 */ |
| 294 | ushort mios_mdasm14br; |
| 295 | ushort mios_mdasm14scrd, mdasm14scr; |
| 296 | ushort mios_mdasm15ar; /* mdasm15 */ |
| 297 | ushort mios_mdasm15br; |
| 298 | ushort mios_mdasm15scrd, mdasm15scr; |
| 299 | ushort mios_mpwmsm16perr; /* mpwmsm16 */ |
| 300 | ushort mios_mpwmsm16pulr; |
| 301 | ushort mios_mpwmsm16cntr; |
| 302 | ushort mios_mpwmsm16scr; |
| 303 | ushort mios_mpwmsm17perr; /* mpwmsm17 */ |
| 304 | ushort mios_mpwmsm17pulr; |
| 305 | ushort mios_mpwmsm17cntr; |
| 306 | ushort mios_mpwmsm17scr; |
| 307 | ushort mios_mpwmsm18perr; /* mpwmsm18 */ |
| 308 | ushort mios_mpwmsm18pulr; |
| 309 | ushort mios_mpwmsm18cntr; |
| 310 | ushort mios_mpwmsm18scr; |
| 311 | ushort mios_mpwmsm19perr; /* mpwmsm19 */ |
| 312 | ushort mios_mpwmsm19pulr; |
| 313 | ushort mios_mpwmsm19cntr; |
| 314 | ushort mios_mpwmsm19scr; |
| 315 | char res3[16]; |
| 316 | ushort mios_mmcsm22cnt; /* mmcsm22 */ |
| 317 | ushort mios_mmcsm22mlr; |
| 318 | ushort mios_mmcsm22scrd, mmcsm22scr; |
| 319 | char res4[32]; |
| 320 | ushort mios_mdasm27ar; /* mdasm27 */ |
| 321 | ushort mios_mdasm27br; |
| 322 | ushort mios_mdasm27scrd, mdasm27scr; |
| 323 | ushort mios_mdasm28ar; /*mdasm28 */ |
| 324 | ushort mios_mdasm28br; |
| 325 | ushort mios_mdasm28scrd, mdasm28scr; |
| 326 | ushort mios_mdasm29ar; /* mdasm29 */ |
| 327 | ushort mios_mdasm29br; |
| 328 | ushort mios_mdasm29scrd, mdasm29scr; |
| 329 | ushort mios_mdasm30ar; /* mdasm30 */ |
| 330 | ushort mios_mdasm30br; |
| 331 | ushort mios_mdasm30scrd, mdasm30scr; |
| 332 | ushort mios_mdasm31ar; /* mdasm31 */ |
| 333 | ushort mios_mdasm31br; |
| 334 | ushort mios_mdasm31scrd, mdasm31scr; |
| 335 | ushort mios_mpiosm32dr; |
| 336 | ushort mios_mpiosm32ddr; |
| 337 | char res5[1788]; |
| 338 | ushort mios_mios1tpcr; |
| 339 | char mios_res13[2]; |
| 340 | ushort mios_mios1vnr; |
| 341 | ushort mios_mios1mcr; |
| 342 | char res6[12]; |
| 343 | ushort mios_res42z; |
| 344 | ushort mios_mcpsmscr; |
| 345 | char res7[1000]; |
| 346 | ushort mios_mios1sr0; |
| 347 | char res12[2]; |
| 348 | ushort mios_mios1er0; |
| 349 | ushort mios_mios1rpr0; |
| 350 | char res8[40]; |
| 351 | ushort mios_mios1lvl0; |
| 352 | char res9[14]; |
| 353 | ushort mios_mios1sr1; |
| 354 | char res10[2]; |
| 355 | ushort mios_mios1er1; |
| 356 | ushort mios_mios1rpr1; |
| 357 | char res11[40]; |
| 358 | ushort mios_mios1lvl1; |
| 359 | char res13[1038]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 360 | } mios5xx_t; |
| 361 | |
| 362 | /* Toucan Module |
| 363 | */ |
| 364 | typedef struct tcan { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 365 | ushort tcan_tcnmcr; |
| 366 | ushort tcan_cantcr; |
| 367 | ushort tcan_canicr; |
| 368 | u_char tcan_canctrl0; |
| 369 | u_char tcan_canctrl1; |
| 370 | u_char tcan_presdiv; |
| 371 | u_char tcan_canctrl2; |
| 372 | ushort tcan_timer; |
| 373 | char res1[4]; |
| 374 | ushort tcan_rxgmskhi; |
| 375 | ushort tcan_rxgmsklo; |
| 376 | ushort tcan_rx14mskhi; |
| 377 | ushort tcan_rx14msklo; |
| 378 | ushort tcan_rx15mskhi; |
| 379 | ushort tcan_rx15msklo; |
| 380 | char res2[4]; |
| 381 | ushort tcan_estat; |
| 382 | ushort tcan_imask; |
| 383 | ushort tcan_iflag; |
| 384 | u_char tcan_rxectr; |
| 385 | u_char tcan_txectr; |
| 386 | char res3[88]; |
| 387 | struct { |
| 388 | ushort scr; |
| 389 | ushort id_high; |
| 390 | ushort id_low; |
| 391 | u_char data[8]; |
| 392 | char res4[2]; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 393 | } tcan_mbuff[16]; |
| 394 | char res5[640]; |
| 395 | } tcan5xx_t; |
| 396 | |
| 397 | /* UIMB |
| 398 | */ |
| 399 | typedef struct uimb { |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 400 | uint uimb_umcr; |
| 401 | char res1[12]; |
| 402 | uint uimb_utstcreg; |
| 403 | char res2[12]; |
| 404 | uint uimb_uipend; |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 405 | } uimb5xx_t; |
| 406 | |
| 407 | |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 408 | /* Internal Memory Map MPC555 |
| 409 | */ |
| 410 | typedef struct immap { |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 411 | char res1[262144]; /* CMF Flash A 256 Kbytes */ |
| 412 | char res2[196608]; /* CMF Flash B 192 Kbytes */ |
| 413 | char res3[2670592]; /* Reserved for Flash */ |
| 414 | sysconf5xx_t im_siu_conf; /* SIU Configuration */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 415 | memctl5xx_t im_memctl; /* Memory Controller */ |
| 416 | sit5xx_t im_sit; /* System Integration Timers */ |
| 417 | car5xx_t im_clkrst; /* Clocks and Reset */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 418 | sitk5xx_t im_sitk; /* System Integration Timer Keys*/ |
| 419 | cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 420 | fl5xx_t im_fla; /* Flash Module A */ |
| 421 | fl5xx_t im_flb; /* Flash Module B */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 422 | char res4[14208]; /* Reserved for SIU */ |
| 423 | dprc5xx_t im_dprc; /* Dpram Control Register */ |
| 424 | char res5[8180]; /* Reserved */ |
| 425 | char dptram[6144]; /* Dptram */ |
| 426 | char res6[2048]; /* Reserved */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 427 | tpu5xx_t im_tpua; /* Time Proessing Unit A */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 428 | tpu5xx_t im_tpub; /* Time Processing Unit B */ |
| 429 | qadc5xx_t im_qadca; /* QADC A */ |
| 430 | qadc5xx_t im_qadcb; /* QADC B */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 431 | qsmcm5xx_t im_qsmcm; /* SCI and SPI */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 432 | mios5xx_t im_mios; /* MIOS */ |
| 433 | tcan5xx_t im_tcana; /* Toucan A */ |
| 434 | tcan5xx_t im_tcanb; /* Toucan B */ |
| 435 | char res7[1792]; /* Reserved */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 436 | uimb5xx_t im_uimb; /* UIMB */ |
wdenk | 359733b | 2003-03-31 17:27:09 +0000 | [diff] [blame] | 437 | } immap_t; |
| 438 | |
| 439 | #endif /* __IMMAP_5XX__ */ |