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git01.mediatek.com / filogic / uboot / 9569c93fc7e7692ab84a060c3acb89e0d7714b2a / . / board / sielaff / imx6dl-sielaff / imx6dl-sielaff.c
blob: 4da084ed91cbbc31afd5c5114a90c0d68f28bbf1 [file] [log] [blame]
Frieder Schrempf9569c932024-02-15 15:00:35 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6#include <compiler.h>
7#include <asm/arch/sys_proto.h>
8#include <asm/arch/clock.h>
9#include <asm/arch/crm_regs.h>
10#include <asm/arch/mx6-pins.h>
11#include <asm/io.h>
12#include <init.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16static const iomux_v3_cfg_t nfc_pads[] = {
17 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
18 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
19 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
20 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
21 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
22 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
23 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
24 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
25 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
26 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
27 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
28 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
29 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
30 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
31 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
32 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
33 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
34 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
35 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
36};
37
38int dram_init(void)
39{
40 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
41 return 0;
42}
43
44static void setup_gpmi_nand(void)
45{
46 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
47
48 /* config gpmi nand iomux */
49 imx_iomux_v3_setup_multiple_pads(nfc_pads,
50 ARRAY_SIZE(nfc_pads));
51
52 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
53 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
54
55 /* config gpmi and bch clock to 100 MHz */
56 clrsetbits_le32(&mxc_ccm->cs2cdr,
57 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
58 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
59 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
60 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
61 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
62 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
63
64 /* enable ENFC_CLK_ROOT clock */
65 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
66
67 /* enable gpmi and bch clock gating */
68 setbits_le32(&mxc_ccm->CCGR4,
69 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
70 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
71 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
72 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
73 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
74
75 /* enable apbh clock gating */
76 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
77}
78
79int board_init(void)
80{
81 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
82 u32 reg;
83
84 setup_gpmi_nand();
85
86 /* Enable SPI2 clock */
87 enable_spi_clk(true, 1);
88
89 /*
90 * Configure clock output for USB hub
91 * 1. Disabling CLK01 and CLK02
92 */
93 clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKOL_EN);
94 clrbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
95
96 /*
97 * 2. Setting ccm timer - osc_clk (24 MHz) divide by 2 -> 12 Mhz
98 * CLK02_DIV: 001b CLK02_SEL: 01110b -> 0010 1110b -> 0x2e
99 */
100 reg = readl(&mxc_ccm->ccosr);
101 reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
102 reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
103 reg |= (0x2e << MXC_CCM_CCOSR_CKO2_SEL_OFFSET);
104 writel(reg, &mxc_ccm->ccosr);
105
106 /* 3. Enabling CLK02 on output CCM_CLK01 */
107 setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CLK_OUT_SEL);
108 setbits_le32(&mxc_ccm->ccosr, MXC_CCM_CCOSR_CKO2_EN_OFFSET);
109
110 return 0;
111}