blob: 42070d76366e8465a84baf3e90a7e95bff429a62 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
wdenk9ca7bbc2004-10-09 23:25:58 +00002 * MPC823 and PXA LCD Controller
wdenkfe8c2802002-11-03 00:38:21 +00003 *
4 * Modeled after video interface by Paolo Scaffardi
5 *
6 *
7 * (C) Copyright 2001
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk9ca7bbc2004-10-09 23:25:58 +000020 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkfe8c2802002-11-03 00:38:21 +000021 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef _LCD_H_
30#define _LCD_H_
31
wdenk4e112c12003-06-03 23:54:09 +000032extern char lcd_is_enabled;
33
wdenk9ca7bbc2004-10-09 23:25:58 +000034extern int lcd_line_length;
35extern int lcd_color_fg;
36extern int lcd_color_bg;
37
38/*
39 * Frame buffer memory information
40 */
41extern void *lcd_base; /* Start of framebuffer memory */
42extern void *lcd_console_address; /* Start of console buffer */
43
44extern short console_col;
45extern short console_row;
Alessandro Rubini465c45a2009-07-19 17:52:27 +020046extern struct vidinfo panel_info;
47
48extern void lcd_ctrl_init (void *lcdbase);
49extern void lcd_enable (void);
50
51/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
52extern void lcd_setcolreg (ushort regno,
53 ushort red, ushort green, ushort blue);
54extern void lcd_initcolregs (void);
55
56/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
57extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
Anatolij Gustschin7a49e6f2012-04-27 04:38:06 +000058extern int bmp_display(ulong addr, int x, int y);
wdenk9ca7bbc2004-10-09 23:25:58 +000059
60#if defined CONFIG_MPC823
61/*
62 * LCD controller stucture for MPC823 CPU
63 */
64typedef struct vidinfo {
65 ushort vl_col; /* Number of columns (i.e. 640) */
66 ushort vl_row; /* Number of rows (i.e. 480) */
67 ushort vl_width; /* Width of display area in millimeters */
68 ushort vl_height; /* Height of display area in millimeters */
69
70 /* LCD configuration register */
71 u_char vl_clkp; /* Clock polarity */
72 u_char vl_oep; /* Output Enable polarity */
73 u_char vl_hsp; /* Horizontal Sync polarity */
74 u_char vl_vsp; /* Vertical Sync polarity */
75 u_char vl_dp; /* Data polarity */
76 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
77 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
78 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
79 u_char vl_clor; /* Color, 0 = mono, 1 = color */
80 u_char vl_tft; /* 0 = passive, 1 = TFT */
81
82 /* Horizontal control register. Timing from data sheet */
83 ushort vl_wbl; /* Wait between lines */
84
85 /* Vertical control register */
86 u_char vl_vpw; /* Vertical sync pulse width */
87 u_char vl_lcdac; /* LCD AC timing */
88 u_char vl_wbf; /* Wait between frames */
89} vidinfo_t;
90
Marek Vasut85cc88a2011-11-26 07:20:07 +010091#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
92 defined CONFIG_CPU_MONAHANS
wdenk9ca7bbc2004-10-09 23:25:58 +000093/*
94 * PXA LCD DMA descriptor
95 */
96struct pxafb_dma_descriptor {
97 u_long fdadr; /* Frame descriptor address register */
98 u_long fsadr; /* Frame source address register */
99 u_long fidr; /* Frame ID register */
100 u_long ldcmd; /* Command register */
101};
102
103/*
104 * PXA LCD info
105 */
106struct pxafb_info {
107
108 /* Misc registers */
109 u_long reg_lccr3;
110 u_long reg_lccr2;
111 u_long reg_lccr1;
112 u_long reg_lccr0;
113 u_long fdadr0;
114 u_long fdadr1;
115
116 /* DMA descriptors */
117 struct pxafb_dma_descriptor * dmadesc_fblow;
118 struct pxafb_dma_descriptor * dmadesc_fbhigh;
119 struct pxafb_dma_descriptor * dmadesc_palette;
120
121 u_long screen; /* physical address of frame buffer */
122 u_long palette; /* physical address of palette memory */
123 u_int palette_size;
124};
125
126/*
127 * LCD controller stucture for PXA CPU
128 */
129typedef struct vidinfo {
130 ushort vl_col; /* Number of columns (i.e. 640) */
131 ushort vl_row; /* Number of rows (i.e. 480) */
132 ushort vl_width; /* Width of display area in millimeters */
133 ushort vl_height; /* Height of display area in millimeters */
134
135 /* LCD configuration register */
136 u_char vl_clkp; /* Clock polarity */
137 u_char vl_oep; /* Output Enable polarity */
138 u_char vl_hsp; /* Horizontal Sync polarity */
139 u_char vl_vsp; /* Vertical Sync polarity */
140 u_char vl_dp; /* Data polarity */
141 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
142 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
143 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
144 u_char vl_clor; /* Color, 0 = mono, 1 = color */
145 u_char vl_tft; /* 0 = passive, 1 = TFT */
146
147 /* Horizontal control register. Timing from data sheet */
148 ushort vl_hpw; /* Horz sync pulse width */
149 u_char vl_blw; /* Wait before of line */
150 u_char vl_elw; /* Wait end of line */
151
152 /* Vertical control register. */
153 u_char vl_vpw; /* Vertical sync pulse width */
154 u_char vl_bfw; /* Wait before of frame */
155 u_char vl_efw; /* Wait end of frame */
156
157 /* PXA LCD controller params */
158 struct pxafb_info pxa;
159} vidinfo_t;
160
Bo Shen8dd55282012-05-25 00:59:58 +0000161#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
Stelian Popf6f86652008-05-09 21:57:18 +0200162
163typedef struct vidinfo {
Marek Vasut21e69c12011-10-24 23:41:00 +0000164 ushort vl_col; /* Number of columns (i.e. 640) */
165 ushort vl_row; /* Number of rows (i.e. 480) */
Stelian Popf6f86652008-05-09 21:57:18 +0200166 u_long vl_clk; /* pixel clock in ps */
167
168 /* LCD configuration register */
169 u_long vl_sync; /* Horizontal / vertical sync */
170 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
171 u_long vl_tft; /* 0 = passive, 1 = TFT */
Alexander Stein7fd4ea52010-07-20 08:55:40 +0200172 u_long vl_cont_pol_low; /* contrast polarity is low */
Bo Shen8dd55282012-05-25 00:59:58 +0000173 u_long vl_clk_pol; /* clock polarity */
Stelian Popf6f86652008-05-09 21:57:18 +0200174
175 /* Horizontal control register. */
176 u_long vl_hsync_len; /* Length of horizontal sync */
177 u_long vl_left_margin; /* Time from sync to picture */
178 u_long vl_right_margin; /* Time from picture to sync */
179
180 /* Vertical control register. */
181 u_long vl_vsync_len; /* Length of vertical sync */
182 u_long vl_upper_margin; /* Time from sync to picture */
183 u_long vl_lower_margin; /* Time from picture to sync */
184
185 u_long mmio; /* Memory mapped registers */
186} vidinfo_t;
187
Donghwa Lee0e6f77d2012-04-05 19:36:15 +0000188#elif defined(CONFIG_EXYNOS_FB)
189
190enum {
191 FIMD_RGB_INTERFACE = 1,
192 FIMD_CPU_INTERFACE = 2,
193};
194
Donghwa Lee37980dd2012-05-09 19:23:46 +0000195enum exynos_fb_rgb_mode_t {
196 MODE_RGB_P = 0,
197 MODE_BGR_P = 1,
198 MODE_RGB_S = 2,
199 MODE_BGR_S = 3,
200};
201
Donghwa Lee0e6f77d2012-04-05 19:36:15 +0000202typedef struct vidinfo {
203 ushort vl_col; /* Number of columns (i.e. 640) */
204 ushort vl_row; /* Number of rows (i.e. 480) */
205 ushort vl_width; /* Width of display area in millimeters */
206 ushort vl_height; /* Height of display area in millimeters */
207
208 /* LCD configuration register */
209 u_char vl_freq; /* Frequency */
210 u_char vl_clkp; /* Clock polarity */
211 u_char vl_oep; /* Output Enable polarity */
212 u_char vl_hsp; /* Horizontal Sync polarity */
213 u_char vl_vsp; /* Vertical Sync polarity */
214 u_char vl_dp; /* Data polarity */
215 u_char vl_bpix; /* Bits per pixel */
216
217 /* Horizontal control register. Timing from data sheet */
218 u_char vl_hspw; /* Horz sync pulse width */
219 u_char vl_hfpd; /* Wait before of line */
220 u_char vl_hbpd; /* Wait end of line */
221
222 /* Vertical control register. */
223 u_char vl_vspw; /* Vertical sync pulse width */
224 u_char vl_vfpd; /* Wait before of frame */
225 u_char vl_vbpd; /* Wait end of frame */
226 u_char vl_cmd_allow_len; /* Wait end of frame */
227
228 void (*cfg_gpio)(void);
229 void (*backlight_on)(unsigned int onoff);
230 void (*reset_lcd)(void);
231 void (*lcd_power_on)(void);
232 void (*cfg_ldo)(void);
233 void (*enable_ldo)(unsigned int onoff);
234 void (*mipi_power)(void);
235 void (*backlight_reset)(void);
236
237 unsigned int win_id;
238 unsigned int init_delay;
239 unsigned int power_on_delay;
240 unsigned int reset_delay;
241 unsigned int interface_mode;
242 unsigned int mipi_enabled;
Donghwa Leebe91a412012-07-02 01:16:05 +0000243 unsigned int dp_enabled;
Donghwa Lee0e6f77d2012-04-05 19:36:15 +0000244 unsigned int cs_setup;
245 unsigned int wr_setup;
246 unsigned int wr_act;
247 unsigned int wr_hold;
Donghwa Lee37980dd2012-05-09 19:23:46 +0000248 unsigned int logo_on;
249 unsigned int logo_width;
250 unsigned int logo_height;
251 unsigned long logo_addr;
252 unsigned int rgb_mode;
253 unsigned int resolution;
Donghwa Lee0e6f77d2012-04-05 19:36:15 +0000254
255 /* parent clock name(MPLL, EPLL or VPLL) */
256 unsigned int pclk_name;
257 /* ratio value for source clock from parent clock. */
258 unsigned int sclk_div;
259
260 unsigned int dual_lcd_enabled;
261
262} vidinfo_t;
263
264void init_panel_info(vidinfo_t *vid);
265
Guennadi Liakhovetski332d0b52009-02-06 10:37:53 +0100266#else
267
268typedef struct vidinfo {
269 ushort vl_col; /* Number of columns (i.e. 160) */
270 ushort vl_row; /* Number of rows (i.e. 100) */
271
272 u_char vl_bpix; /* Bits per pixel, 0 = 1 */
273
274 ushort *cmap; /* Pointer to the colormap */
275
276 void *priv; /* Pointer to driver-specific data */
277} vidinfo_t;
278
Marek Vasut85cc88a2011-11-26 07:20:07 +0100279#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
wdenk9ca7bbc2004-10-09 23:25:58 +0000280
Alessandro Rubini249ce8a2009-07-21 14:09:45 +0200281extern vidinfo_t panel_info;
282
wdenkfe8c2802002-11-03 00:38:21 +0000283/* Video functions */
284
wdenk9ca7bbc2004-10-09 23:25:58 +0000285#if defined(CONFIG_RBC823)
286void lcd_disable (void);
287#endif
288
289
wdenk0811ded2004-06-25 23:35:58 +0000290/* int lcd_init (void *lcdbase); */
wdenkfe8c2802002-11-03 00:38:21 +0000291void lcd_putc (const char c);
292void lcd_puts (const char *s);
293void lcd_printf (const char *fmt, ...);
Che-Liang Chiou2444b172011-10-20 23:07:03 +0000294void lcd_clear(void);
295int lcd_display_bitmap(ulong bmp_image, int x, int y);
wdenkfe8c2802002-11-03 00:38:21 +0000296
Haavard Skinnemoenddbcf952008-09-01 16:21:22 +0200297/* Allow boards to customize the information displayed */
298void lcd_show_board_info(void);
wdenk9ca7bbc2004-10-09 23:25:58 +0000299
300/************************************************************************/
301/* ** BITMAP DISPLAY SUPPORT */
302/************************************************************************/
Jon Loeliger2517d972007-07-09 17:15:49 -0500303#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
wdenk9ca7bbc2004-10-09 23:25:58 +0000304# include <bmp_layout.h>
305# include <asm/byteorder.h>
Jon Loeliger2517d972007-07-09 17:15:49 -0500306#endif
wdenk9ca7bbc2004-10-09 23:25:58 +0000307
wdenk9ca7bbc2004-10-09 23:25:58 +0000308/*
309 * Information about displays we are using. This is for configuring
310 * the LCD controller and memory allocation. Someone has to know what
311 * is connected, as we can't autodetect anything.
312 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200313#define CONFIG_SYS_HIGH 0 /* Pins are active high */
314#define CONFIG_SYS_LOW 1 /* Pins are active low */
wdenk9ca7bbc2004-10-09 23:25:58 +0000315
316#define LCD_MONOCHROME 0
317#define LCD_COLOR2 1
318#define LCD_COLOR4 2
319#define LCD_COLOR8 3
320#define LCD_COLOR16 4
321
322/*----------------------------------------------------------------------*/
wdenk2b9d1862005-07-04 00:03:16 +0000323#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
wdenk9ca7bbc2004-10-09 23:25:58 +0000324# define LCD_INFO_X 0
325# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
326#elif defined(CONFIG_LCD_LOGO)
327# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
328# define LCD_INFO_Y (VIDEO_FONT_HEIGHT)
329#else
330# define LCD_INFO_X (VIDEO_FONT_WIDTH)
331# define LCD_INFO_Y (VIDEO_FONT_HEIGHT)
332#endif
333
334/* Default to 8bpp if bit depth not specified */
335#ifndef LCD_BPP
336# define LCD_BPP LCD_COLOR8
337#endif
338#ifndef LCD_DF
339# define LCD_DF 1
340#endif
341
342/* Calculate nr. of bits per pixel and nr. of colors */
343#define NBITS(bit_code) (1 << (bit_code))
344#define NCOLORS(bit_code) (1 << NBITS(bit_code))
345
346/************************************************************************/
347/* ** CONSOLE CONSTANTS */
348/************************************************************************/
349#if LCD_BPP == LCD_MONOCHROME
350
351/*
352 * Simple black/white definitions
353 */
354# define CONSOLE_COLOR_BLACK 0
355# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
356
357#elif LCD_BPP == LCD_COLOR8
358
359/*
360 * 8bpp color definitions
361 */
362# define CONSOLE_COLOR_BLACK 0
363# define CONSOLE_COLOR_RED 1
364# define CONSOLE_COLOR_GREEN 2
365# define CONSOLE_COLOR_YELLOW 3
366# define CONSOLE_COLOR_BLUE 4
367# define CONSOLE_COLOR_MAGENTA 5
368# define CONSOLE_COLOR_CYAN 6
369# define CONSOLE_COLOR_GREY 14
370# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
371
372#else
373
374/*
375 * 16bpp color definitions
376 */
377# define CONSOLE_COLOR_BLACK 0x0000
378# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
379
380#endif /* color definitions */
381
wdenk9ca7bbc2004-10-09 23:25:58 +0000382/************************************************************************/
383#ifndef PAGE_SIZE
384# define PAGE_SIZE 4096
385#endif
386
387/************************************************************************/
388/* ** CONSOLE DEFINITIONS & FUNCTIONS */
389/************************************************************************/
wdenk2b9d1862005-07-04 00:03:16 +0000390#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
wdenk9ca7bbc2004-10-09 23:25:58 +0000391# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \
392 / VIDEO_FONT_HEIGHT)
393#else
394# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT)
395#endif
396
397#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH)
398#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length)
399#define CONSOLE_ROW_FIRST (lcd_console_address)
400#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE)
401#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \
402 - CONSOLE_ROW_SIZE)
403#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
404#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
405
406#if LCD_BPP == LCD_MONOCHROME
407# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
408 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
Mark Jackson8ef053f2009-07-21 11:18:44 +0100409#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
wdenk9ca7bbc2004-10-09 23:25:58 +0000410# define COLOR_MASK(c) (c)
411#else
412# error Unsupported LCD BPP.
wdenkfe8c2802002-11-03 00:38:21 +0000413#endif
wdenk9ca7bbc2004-10-09 23:25:58 +0000414
415/************************************************************************/
416
417#endif /* _LCD_H_ */