Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 1 | /* |
| 2 | * *************************************************************************** |
| 3 | * Copyright (C) 2015 Marvell International Ltd. |
| 4 | * *************************************************************************** |
| 5 | * This program is free software: you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the Free |
| 7 | * Software Foundation, either version 2 of the License, or any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | * *************************************************************************** |
| 17 | */ |
| 18 | /* pcie_advk.c |
| 19 | * |
| 20 | * Ported from Linux driver - driver/pci/host/pci-aardvark.c |
| 21 | * |
| 22 | * Author: Victor Gu <xigu@marvell.com> |
| 23 | * Hezi Shahmoon <hezi.shahmoon@marvell.com> |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include <common.h> |
| 28 | #include <dm.h> |
| 29 | #include <pci.h> |
| 30 | #include <asm/io.h> |
| 31 | #include <asm-generic/gpio.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 32 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 33 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 34 | #include <linux/delay.h> |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 35 | #include <linux/ioport.h> |
| 36 | |
| 37 | /* PCIe core registers */ |
| 38 | #define PCIE_CORE_CMD_STATUS_REG 0x4 |
| 39 | #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) |
| 40 | #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) |
| 41 | #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) |
| 42 | #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 |
| 43 | #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) |
| 44 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) |
| 45 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 |
| 46 | #define PCIE_CORE_LINK_TRAINING BIT(5) |
| 47 | #define PCIE_CORE_ERR_CAPCTL_REG 0x118 |
| 48 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) |
| 49 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) |
| 50 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7) |
| 51 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8) |
| 52 | |
| 53 | /* PIO registers base address and register offsets */ |
| 54 | #define PIO_BASE_ADDR 0x4000 |
| 55 | #define PIO_CTRL (PIO_BASE_ADDR + 0x0) |
| 56 | #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) |
| 57 | #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) |
| 58 | #define PIO_STAT (PIO_BASE_ADDR + 0x4) |
| 59 | #define PIO_COMPLETION_STATUS_SHIFT 7 |
| 60 | #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) |
| 61 | #define PIO_COMPLETION_STATUS_OK 0 |
| 62 | #define PIO_COMPLETION_STATUS_UR 1 |
| 63 | #define PIO_COMPLETION_STATUS_CRS 2 |
| 64 | #define PIO_COMPLETION_STATUS_CA 4 |
| 65 | #define PIO_NON_POSTED_REQ BIT(10) |
| 66 | #define PIO_ERR_STATUS BIT(11) |
| 67 | #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) |
| 68 | #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) |
| 69 | #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) |
| 70 | #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) |
| 71 | #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) |
| 72 | #define PIO_START (PIO_BASE_ADDR + 0x1c) |
| 73 | #define PIO_ISR (PIO_BASE_ADDR + 0x20) |
| 74 | |
| 75 | /* Aardvark Control registers */ |
| 76 | #define CONTROL_BASE_ADDR 0x4800 |
| 77 | #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) |
| 78 | #define PCIE_GEN_SEL_MSK 0x3 |
| 79 | #define PCIE_GEN_SEL_SHIFT 0x0 |
| 80 | #define SPEED_GEN_1 0 |
| 81 | #define SPEED_GEN_2 1 |
| 82 | #define SPEED_GEN_3 2 |
| 83 | #define IS_RC_MSK 1 |
| 84 | #define IS_RC_SHIFT 2 |
| 85 | #define LANE_CNT_MSK 0x18 |
| 86 | #define LANE_CNT_SHIFT 0x3 |
| 87 | #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) |
| 88 | #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) |
| 89 | #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) |
| 90 | #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) |
| 91 | #define LINK_TRAINING_EN BIT(6) |
| 92 | #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) |
| 93 | #define PCIE_CORE_CTRL2_RESERVED 0x7 |
| 94 | #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) |
| 95 | #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) |
| 96 | #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6) |
| 97 | |
| 98 | /* LMI registers base address and register offsets */ |
| 99 | #define LMI_BASE_ADDR 0x6000 |
| 100 | #define CFG_REG (LMI_BASE_ADDR + 0x0) |
| 101 | #define LTSSM_SHIFT 24 |
| 102 | #define LTSSM_MASK 0x3f |
| 103 | #define LTSSM_L0 0x10 |
| 104 | |
| 105 | /* PCIe core controller registers */ |
| 106 | #define CTRL_CORE_BASE_ADDR 0x18000 |
| 107 | #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) |
| 108 | #define CTRL_MODE_SHIFT 0x0 |
| 109 | #define CTRL_MODE_MASK 0x1 |
| 110 | #define PCIE_CORE_MODE_DIRECT 0x0 |
| 111 | #define PCIE_CORE_MODE_COMMAND 0x1 |
| 112 | |
| 113 | /* Transaction types */ |
| 114 | #define PCIE_CONFIG_RD_TYPE0 0x8 |
| 115 | #define PCIE_CONFIG_RD_TYPE1 0x9 |
| 116 | #define PCIE_CONFIG_WR_TYPE0 0xa |
| 117 | #define PCIE_CONFIG_WR_TYPE1 0xb |
| 118 | |
| 119 | /* PCI_BDF shifts 8bit, so we need extra 4bit shift */ |
| 120 | #define PCIE_BDF(dev) (dev << 4) |
| 121 | #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) |
| 122 | #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) |
| 123 | #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) |
| 124 | #define PCIE_CONF_REG(reg) ((reg) & 0xffc) |
| 125 | #define PCIE_CONF_ADDR(bus, devfn, where) \ |
| 126 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ |
| 127 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) |
| 128 | |
| 129 | /* PCIe Retries & Timeout definitions */ |
| 130 | #define MAX_RETRIES 10 |
| 131 | #define PIO_WAIT_TIMEOUT 100 |
| 132 | #define LINK_WAIT_TIMEOUT 100000 |
| 133 | |
| 134 | #define CFG_RD_UR_VAL 0xFFFFFFFF |
| 135 | #define CFG_RD_CRS_VAL 0xFFFF0001 |
| 136 | |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 137 | /** |
| 138 | * struct pcie_advk - Advk PCIe controller state |
| 139 | * |
| 140 | * @reg_base: The base address of the register space. |
| 141 | * @first_busno: This driver supports multiple PCIe controllers. |
| 142 | * first_busno stores the bus number of the PCIe root-port |
| 143 | * number which may vary depending on the PCIe setup |
| 144 | * (PEX switches etc). |
| 145 | * @device: The pointer to PCI uclass device. |
| 146 | */ |
| 147 | struct pcie_advk { |
| 148 | void *base; |
| 149 | int first_busno; |
| 150 | struct udevice *dev; |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 151 | struct gpio_desc reset_gpio; |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) |
| 155 | { |
| 156 | writel(val, pcie->base + reg); |
| 157 | } |
| 158 | |
| 159 | static inline uint advk_readl(struct pcie_advk *pcie, uint reg) |
| 160 | { |
| 161 | return readl(pcie->base + reg); |
| 162 | } |
| 163 | |
| 164 | /** |
| 165 | * pcie_advk_addr_valid() - Check for valid bus address |
| 166 | * |
| 167 | * @bdf: The PCI device to access |
| 168 | * @first_busno: Bus number of the PCIe controller root complex |
| 169 | * |
| 170 | * Return: 1 on valid, 0 on invalid |
| 171 | */ |
| 172 | static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) |
| 173 | { |
| 174 | /* |
| 175 | * In PCIE-E only a single device (0) can exist |
| 176 | * on the local bus. Beyound the local bus, there might be |
| 177 | * a Switch and everything is possible. |
| 178 | */ |
| 179 | if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0)) |
| 180 | return 0; |
| 181 | |
| 182 | return 1; |
| 183 | } |
| 184 | |
| 185 | /** |
| 186 | * pcie_advk_wait_pio() - Wait for PIO access to be accomplished |
| 187 | * |
| 188 | * @pcie: The PCI device to access |
| 189 | * |
| 190 | * Wait up to 1 micro second for PIO access to be accomplished. |
| 191 | * |
| 192 | * Return 1 (true) if PIO access is accomplished. |
| 193 | * Return 0 (false) if PIO access is timed out. |
| 194 | */ |
| 195 | static int pcie_advk_wait_pio(struct pcie_advk *pcie) |
| 196 | { |
| 197 | uint start, isr; |
| 198 | uint count; |
| 199 | |
| 200 | for (count = 0; count < MAX_RETRIES; count++) { |
| 201 | start = advk_readl(pcie, PIO_START); |
| 202 | isr = advk_readl(pcie, PIO_ISR); |
| 203 | if (!start && isr) |
| 204 | return 1; |
| 205 | /* |
| 206 | * Do not check the PIO state too frequently, |
| 207 | * 100us delay is appropriate. |
| 208 | */ |
| 209 | udelay(PIO_WAIT_TIMEOUT); |
| 210 | } |
| 211 | |
| 212 | dev_err(pcie->dev, "config read/write timed out\n"); |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * pcie_advk_check_pio_status() - Validate PIO status and get the read result |
| 218 | * |
| 219 | * @pcie: Pointer to the PCI bus |
| 220 | * @read: Read from or write to configuration space - true(read) false(write) |
| 221 | * @read_val: Pointer to the read result, only valid when read is true |
| 222 | * |
| 223 | */ |
| 224 | static int pcie_advk_check_pio_status(struct pcie_advk *pcie, |
| 225 | bool read, |
| 226 | uint *read_val) |
| 227 | { |
| 228 | uint reg; |
| 229 | unsigned int status; |
| 230 | char *strcomp_status, *str_posted; |
| 231 | |
| 232 | reg = advk_readl(pcie, PIO_STAT); |
| 233 | status = (reg & PIO_COMPLETION_STATUS_MASK) >> |
| 234 | PIO_COMPLETION_STATUS_SHIFT; |
| 235 | |
| 236 | switch (status) { |
| 237 | case PIO_COMPLETION_STATUS_OK: |
| 238 | if (reg & PIO_ERR_STATUS) { |
| 239 | strcomp_status = "COMP_ERR"; |
| 240 | break; |
| 241 | } |
| 242 | /* Get the read result */ |
| 243 | if (read) |
| 244 | *read_val = advk_readl(pcie, PIO_RD_DATA); |
| 245 | /* No error */ |
| 246 | strcomp_status = NULL; |
| 247 | break; |
| 248 | case PIO_COMPLETION_STATUS_UR: |
| 249 | if (read) { |
| 250 | /* For reading, UR is not an error status. */ |
| 251 | *read_val = CFG_RD_UR_VAL; |
| 252 | strcomp_status = NULL; |
| 253 | } else { |
| 254 | strcomp_status = "UR"; |
| 255 | } |
| 256 | break; |
| 257 | case PIO_COMPLETION_STATUS_CRS: |
| 258 | if (read) { |
| 259 | /* For reading, CRS is not an error status. */ |
| 260 | *read_val = CFG_RD_CRS_VAL; |
| 261 | strcomp_status = NULL; |
| 262 | } else { |
| 263 | strcomp_status = "CRS"; |
| 264 | } |
| 265 | break; |
| 266 | case PIO_COMPLETION_STATUS_CA: |
| 267 | strcomp_status = "CA"; |
| 268 | break; |
| 269 | default: |
| 270 | strcomp_status = "Unknown"; |
| 271 | break; |
| 272 | } |
| 273 | |
| 274 | if (!strcomp_status) |
| 275 | return 0; |
| 276 | |
| 277 | if (reg & PIO_NON_POSTED_REQ) |
| 278 | str_posted = "Non-posted"; |
| 279 | else |
| 280 | str_posted = "Posted"; |
| 281 | |
| 282 | dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", |
| 283 | str_posted, strcomp_status, reg, |
| 284 | advk_readl(pcie, PIO_ADDR_LS)); |
| 285 | |
| 286 | return -EFAULT; |
| 287 | } |
| 288 | |
| 289 | /** |
| 290 | * pcie_advk_read_config() - Read from configuration space |
| 291 | * |
| 292 | * @bus: Pointer to the PCI bus |
| 293 | * @bdf: Identifies the PCIe device to access |
| 294 | * @offset: The offset into the device's configuration space |
| 295 | * @valuep: A pointer at which to store the read value |
| 296 | * @size: Indicates the size of access to perform |
| 297 | * |
| 298 | * Read a value of size @size from offset @offset within the configuration |
| 299 | * space of the device identified by the bus, device & function numbers in @bdf |
| 300 | * on the PCI bus @bus. |
| 301 | * |
| 302 | * Return: 0 on success |
| 303 | */ |
Simon Glass | 2a311e8 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 304 | static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 305 | uint offset, ulong *valuep, |
| 306 | enum pci_size_t size) |
| 307 | { |
| 308 | struct pcie_advk *pcie = dev_get_priv(bus); |
| 309 | uint reg; |
| 310 | int ret; |
| 311 | |
| 312 | dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", |
| 313 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); |
| 314 | |
| 315 | if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { |
| 316 | dev_dbg(pcie->dev, "- out of range\n"); |
| 317 | *valuep = pci_get_ff(size); |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | /* Start PIO */ |
| 322 | advk_writel(pcie, 0, PIO_START); |
| 323 | advk_writel(pcie, 1, PIO_ISR); |
| 324 | |
| 325 | /* Program the control register */ |
| 326 | reg = advk_readl(pcie, PIO_CTRL); |
| 327 | reg &= ~PIO_CTRL_TYPE_MASK; |
| 328 | if (PCI_BUS(bdf) == pcie->first_busno) |
| 329 | reg |= PCIE_CONFIG_RD_TYPE0; |
| 330 | else |
| 331 | reg |= PCIE_CONFIG_RD_TYPE1; |
| 332 | advk_writel(pcie, reg, PIO_CTRL); |
| 333 | |
| 334 | /* Program the address registers */ |
| 335 | reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset); |
| 336 | advk_writel(pcie, reg, PIO_ADDR_LS); |
| 337 | advk_writel(pcie, 0, PIO_ADDR_MS); |
| 338 | |
| 339 | /* Start the transfer */ |
| 340 | advk_writel(pcie, 1, PIO_START); |
| 341 | |
| 342 | if (!pcie_advk_wait_pio(pcie)) |
| 343 | return -EINVAL; |
| 344 | |
| 345 | /* Check PIO status and get the read result */ |
| 346 | ret = pcie_advk_check_pio_status(pcie, true, ®); |
| 347 | if (ret) |
| 348 | return ret; |
| 349 | |
| 350 | dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n", |
| 351 | offset, size, reg); |
| 352 | *valuep = pci_conv_32_to_size(reg, offset, size); |
| 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | /** |
| 358 | * pcie_calc_datastrobe() - Calculate data strobe |
| 359 | * |
| 360 | * @offset: The offset into the device's configuration space |
| 361 | * @size: Indicates the size of access to perform |
| 362 | * |
| 363 | * Calculate data strobe according to offset and size |
| 364 | * |
| 365 | */ |
| 366 | static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size) |
| 367 | { |
| 368 | uint bytes, data_strobe; |
| 369 | |
| 370 | switch (size) { |
| 371 | case PCI_SIZE_8: |
| 372 | bytes = 1; |
| 373 | break; |
| 374 | case PCI_SIZE_16: |
| 375 | bytes = 2; |
| 376 | break; |
| 377 | default: |
| 378 | bytes = 4; |
| 379 | } |
| 380 | |
| 381 | data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3); |
| 382 | |
| 383 | return data_strobe; |
| 384 | } |
| 385 | |
| 386 | /** |
| 387 | * pcie_advk_write_config() - Write to configuration space |
| 388 | * |
| 389 | * @bus: Pointer to the PCI bus |
| 390 | * @bdf: Identifies the PCIe device to access |
| 391 | * @offset: The offset into the device's configuration space |
| 392 | * @value: The value to write |
| 393 | * @size: Indicates the size of access to perform |
| 394 | * |
| 395 | * Write the value @value of size @size from offset @offset within the |
| 396 | * configuration space of the device identified by the bus, device & function |
| 397 | * numbers in @bdf on the PCI bus @bus. |
| 398 | * |
| 399 | * Return: 0 on success |
| 400 | */ |
| 401 | static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, |
| 402 | uint offset, ulong value, |
| 403 | enum pci_size_t size) |
| 404 | { |
| 405 | struct pcie_advk *pcie = dev_get_priv(bus); |
| 406 | uint reg; |
| 407 | |
| 408 | dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", |
| 409 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); |
| 410 | dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", |
| 411 | offset, size, value); |
| 412 | |
| 413 | if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { |
| 414 | dev_dbg(pcie->dev, "- out of range\n"); |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | /* Start PIO */ |
| 419 | advk_writel(pcie, 0, PIO_START); |
| 420 | advk_writel(pcie, 1, PIO_ISR); |
| 421 | |
| 422 | /* Program the control register */ |
| 423 | reg = advk_readl(pcie, PIO_CTRL); |
| 424 | reg &= ~PIO_CTRL_TYPE_MASK; |
| 425 | if (PCI_BUS(bdf) == pcie->first_busno) |
| 426 | reg |= PCIE_CONFIG_WR_TYPE0; |
| 427 | else |
| 428 | reg |= PCIE_CONFIG_WR_TYPE1; |
| 429 | advk_writel(pcie, reg, PIO_CTRL); |
| 430 | |
| 431 | /* Program the address registers */ |
| 432 | reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset); |
| 433 | advk_writel(pcie, reg, PIO_ADDR_LS); |
| 434 | advk_writel(pcie, 0, PIO_ADDR_MS); |
| 435 | dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg); |
| 436 | |
| 437 | /* Program the data register */ |
| 438 | reg = pci_conv_size_to_32(0, value, offset, size); |
| 439 | advk_writel(pcie, reg, PIO_WR_DATA); |
| 440 | dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg); |
| 441 | |
| 442 | /* Program the data strobe */ |
| 443 | reg = pcie_calc_datastrobe(offset, size); |
| 444 | advk_writel(pcie, reg, PIO_WR_DATA_STRB); |
| 445 | dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); |
| 446 | |
| 447 | /* Start the transfer */ |
| 448 | advk_writel(pcie, 1, PIO_START); |
| 449 | |
| 450 | if (!pcie_advk_wait_pio(pcie)) { |
| 451 | dev_dbg(pcie->dev, "- wait pio timeout\n"); |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
| 455 | /* Check PIO status */ |
| 456 | pcie_advk_check_pio_status(pcie, false, ®); |
| 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | /** |
| 462 | * pcie_advk_link_up() - Check if PCIe link is up or not |
| 463 | * |
| 464 | * @pcie: The PCI device to access |
| 465 | * |
| 466 | * Return 1 (true) on link up. |
| 467 | * Return 0 (false) on link down. |
| 468 | */ |
| 469 | static int pcie_advk_link_up(struct pcie_advk *pcie) |
| 470 | { |
| 471 | u32 val, ltssm_state; |
| 472 | |
| 473 | val = advk_readl(pcie, CFG_REG); |
| 474 | ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; |
| 475 | return ltssm_state >= LTSSM_L0; |
| 476 | } |
| 477 | |
| 478 | /** |
| 479 | * pcie_advk_wait_for_link() - Wait for link training to be accomplished |
| 480 | * |
| 481 | * @pcie: The PCI device to access |
| 482 | * |
| 483 | * Wait up to 1 second for link training to be accomplished. |
| 484 | * |
| 485 | * Return 1 (true) if link training ends up with link up success. |
| 486 | * Return 0 (false) if link training ends up with link up failure. |
| 487 | */ |
| 488 | static int pcie_advk_wait_for_link(struct pcie_advk *pcie) |
| 489 | { |
| 490 | int retries; |
| 491 | |
| 492 | /* check if the link is up or not */ |
| 493 | for (retries = 0; retries < MAX_RETRIES; retries++) { |
| 494 | if (pcie_advk_link_up(pcie)) { |
| 495 | printf("PCIE-%d: Link up\n", pcie->first_busno); |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | udelay(LINK_WAIT_TIMEOUT); |
| 500 | } |
| 501 | |
| 502 | printf("PCIE-%d: Link down\n", pcie->first_busno); |
| 503 | |
| 504 | return -ETIMEDOUT; |
| 505 | } |
| 506 | |
| 507 | /** |
| 508 | * pcie_advk_setup_hw() - PCIe initailzation |
| 509 | * |
| 510 | * @pcie: The PCI device to access |
| 511 | * |
| 512 | * Return: 0 on success |
| 513 | */ |
| 514 | static int pcie_advk_setup_hw(struct pcie_advk *pcie) |
| 515 | { |
| 516 | u32 reg; |
| 517 | |
| 518 | /* Set to Direct mode */ |
| 519 | reg = advk_readl(pcie, CTRL_CONFIG_REG); |
| 520 | reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); |
| 521 | reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); |
| 522 | advk_writel(pcie, reg, CTRL_CONFIG_REG); |
| 523 | |
| 524 | /* Set PCI global control register to RC mode */ |
| 525 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
| 526 | reg |= (IS_RC_MSK << IS_RC_SHIFT); |
| 527 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); |
| 528 | |
| 529 | /* Set Advanced Error Capabilities and Control PF0 register */ |
| 530 | reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | |
| 531 | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | |
| 532 | PCIE_CORE_ERR_CAPCTL_ECRC_CHECK | |
| 533 | PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV; |
| 534 | advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); |
| 535 | |
| 536 | /* Set PCIe Device Control and Status 1 PF0 register */ |
| 537 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | |
| 538 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE; |
| 539 | advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); |
| 540 | |
| 541 | /* Program PCIe Control 2 to disable strict ordering */ |
| 542 | reg = PCIE_CORE_CTRL2_RESERVED | |
| 543 | PCIE_CORE_CTRL2_TD_ENABLE; |
| 544 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); |
| 545 | |
| 546 | /* Set GEN2 */ |
| 547 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
| 548 | reg &= ~PCIE_GEN_SEL_MSK; |
| 549 | reg |= SPEED_GEN_2; |
| 550 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); |
| 551 | |
| 552 | /* Set lane X1 */ |
| 553 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
| 554 | reg &= ~LANE_CNT_MSK; |
| 555 | reg |= LANE_COUNT_1; |
| 556 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); |
| 557 | |
| 558 | /* Enable link training */ |
| 559 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
| 560 | reg |= LINK_TRAINING_EN; |
| 561 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); |
| 562 | |
| 563 | /* |
| 564 | * Enable AXI address window location generation: |
| 565 | * When it is enabled, the default outbound window |
| 566 | * configurations (Default User Field: 0xD0074CFC) |
| 567 | * are used to transparent address translation for |
| 568 | * the outbound transactions. Thus, PCIe address |
| 569 | * windows are not required. |
| 570 | */ |
| 571 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); |
| 572 | reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE; |
| 573 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); |
| 574 | |
| 575 | /* |
| 576 | * Bypass the address window mapping for PIO: |
| 577 | * Since PIO access already contains all required |
| 578 | * info over AXI interface by PIO registers, the |
| 579 | * address window is not required. |
| 580 | */ |
| 581 | reg = advk_readl(pcie, PIO_CTRL); |
| 582 | reg |= PIO_CTRL_ADDR_WIN_DISABLE; |
| 583 | advk_writel(pcie, reg, PIO_CTRL); |
| 584 | |
| 585 | /* Start link training */ |
| 586 | reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); |
| 587 | reg |= PCIE_CORE_LINK_TRAINING; |
| 588 | advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); |
| 589 | |
| 590 | /* Wait for PCIe link up */ |
| 591 | if (pcie_advk_wait_for_link(pcie)) |
| 592 | return -ENXIO; |
| 593 | |
| 594 | reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); |
| 595 | reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | |
| 596 | PCIE_CORE_CMD_IO_ACCESS_EN | |
| 597 | PCIE_CORE_CMD_MEM_IO_REQ_EN; |
| 598 | advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); |
| 599 | |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | /** |
| 604 | * pcie_advk_probe() - Probe the PCIe bus for active link |
| 605 | * |
| 606 | * @dev: A pointer to the device being operated on |
| 607 | * |
| 608 | * Probe for an active link on the PCIe bus and configure the controller |
| 609 | * to enable this port. |
| 610 | * |
| 611 | * Return: 0 on success, else -ENODEV |
| 612 | */ |
| 613 | static int pcie_advk_probe(struct udevice *dev) |
| 614 | { |
| 615 | struct pcie_advk *pcie = dev_get_priv(dev); |
| 616 | |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 617 | gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 618 | GPIOD_IS_OUT); |
| 619 | /* |
| 620 | * Issue reset to add-in card through the dedicated GPIO. |
| 621 | * Some boards are connecting the card reset pin to common system |
| 622 | * reset wire and others are using separate GPIO port. |
| 623 | * In the last case we have to release a reset of the addon card |
| 624 | * using this GPIO. |
| 625 | * |
| 626 | * FIX-ME: |
| 627 | * The PCIe RESET signal is not supposed to be released along |
| 628 | * with the SOC RESET signal. It should be lowered as early as |
| 629 | * possible before PCIe PHY initialization. Moreover, the PCIe |
| 630 | * clock should be gated as well. |
| 631 | */ |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 632 | if (dm_gpio_is_valid(&pcie->reset_gpio)) { |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 633 | dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n"); |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 634 | dm_gpio_set_value(&pcie->reset_gpio, 1); |
Pali Rohár | 0130a61 | 2020-08-19 15:57:06 +0200 | [diff] [blame] | 635 | mdelay(200); |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 636 | dm_gpio_set_value(&pcie->reset_gpio, 0); |
Pali Rohár | 5c6edca | 2020-08-25 10:45:04 +0200 | [diff] [blame] | 637 | } else { |
| 638 | dev_warn(pcie->dev, "PCIE Reset on GPIO support is missing\n"); |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 639 | } |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 640 | |
Simon Glass | 75e534b | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 641 | pcie->first_busno = dev_seq(dev); |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 642 | pcie->dev = pci_get_controller(dev); |
| 643 | |
| 644 | return pcie_advk_setup_hw(pcie); |
| 645 | } |
| 646 | |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 647 | static int pcie_advk_remove(struct udevice *dev) |
| 648 | { |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 649 | struct pcie_advk *pcie = dev_get_priv(dev); |
Pali Rohár | ff87699 | 2020-09-22 13:21:38 +0200 | [diff] [blame] | 650 | u32 reg; |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 651 | |
| 652 | if (dm_gpio_is_valid(&pcie->reset_gpio)) |
| 653 | dm_gpio_set_value(&pcie->reset_gpio, 1); |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 654 | |
Pali Rohár | ff87699 | 2020-09-22 13:21:38 +0200 | [diff] [blame] | 655 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
| 656 | reg &= ~LINK_TRAINING_EN; |
| 657 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); |
| 658 | |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 659 | return 0; |
| 660 | } |
| 661 | |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 662 | /** |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 663 | * pcie_advk_of_to_plat() - Translate from DT to device state |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 664 | * |
| 665 | * @dev: A pointer to the device being operated on |
| 666 | * |
| 667 | * Translate relevant data from the device tree pertaining to device @dev into |
| 668 | * state that the driver will later make use of. This state is stored in the |
| 669 | * device's private data structure. |
| 670 | * |
| 671 | * Return: 0 on success, else -EINVAL |
| 672 | */ |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 673 | static int pcie_advk_of_to_plat(struct udevice *dev) |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 674 | { |
| 675 | struct pcie_advk *pcie = dev_get_priv(dev); |
| 676 | |
| 677 | /* Get the register base address */ |
| 678 | pcie->base = (void *)dev_read_addr_index(dev, 0); |
| 679 | if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE) |
| 680 | return -EINVAL; |
| 681 | |
| 682 | return 0; |
| 683 | } |
| 684 | |
| 685 | static const struct dm_pci_ops pcie_advk_ops = { |
| 686 | .read_config = pcie_advk_read_config, |
| 687 | .write_config = pcie_advk_write_config, |
| 688 | }; |
| 689 | |
| 690 | static const struct udevice_id pcie_advk_ids[] = { |
| 691 | { .compatible = "marvell,armada-37xx-pcie" }, |
| 692 | { } |
| 693 | }; |
| 694 | |
| 695 | U_BOOT_DRIVER(pcie_advk) = { |
| 696 | .name = "pcie_advk", |
| 697 | .id = UCLASS_PCI, |
| 698 | .of_match = pcie_advk_ids, |
| 699 | .ops = &pcie_advk_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 700 | .of_to_plat = pcie_advk_of_to_plat, |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 701 | .probe = pcie_advk_probe, |
Pali Rohár | 6a58b97 | 2020-08-19 15:57:07 +0200 | [diff] [blame] | 702 | .remove = pcie_advk_remove, |
| 703 | .flags = DM_FLAG_OS_PREPARE, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 704 | .priv_auto = sizeof(struct pcie_advk), |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 705 | }; |