blob: 27e213f79669f207a0eff3786ddaaaf819afea68 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hud2396512016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Mingkai Hud2396512016-09-07 18:47:28 +08004 */
5
6#include <common.h>
7#include <i2c.h>
8#include <fdt_support.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Mingkai Hud2396512016-09-07 18:47:28 +080010#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/ppa.h>
14#include <asm/arch/soc.h>
Laurentiu Tudor512d13e2018-08-09 15:19:46 +030015#include <asm/arch-fsl-layerscape/fsl_icid.h>
Mingkai Hud2396512016-09-07 18:47:28 +080016#include <hwconfig.h>
17#include <ahci.h>
18#include <mmc.h>
19#include <scsi.h>
20#include <fm_eth.h>
21#include <fsl_csu.h>
22#include <fsl_esdhc.h>
Hou Zhiqiang67b6d0a2016-12-09 16:09:01 +080023#include <power/mc34vr500_pmic.h>
Mingkai Hud2396512016-09-07 18:47:28 +080024#include "cpld.h"
Vinitha Pillai-B57223a47072e2017-03-23 13:48:18 +053025#include <fsl_sec.h>
Mingkai Hud2396512016-09-07 18:47:28 +080026
27DECLARE_GLOBAL_DATA_PTR;
28
Sumit Gargc064fc72017-03-30 09:53:13 +053029int board_early_init_f(void)
30{
31 fsl_lsch2_early_init_f();
32
33 return 0;
34}
35
36#ifndef CONFIG_SPL_BUILD
Mingkai Hud2396512016-09-07 18:47:28 +080037int checkboard(void)
38{
39 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
40 u8 cfg_rcw_src1, cfg_rcw_src2;
41 u16 cfg_rcw_src;
42 u8 sd1refclk_sel;
43
44 puts("Board: LS1046ARDB, boot from ");
45
46 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
47 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
48 cpld_rev_bit(&cfg_rcw_src1);
49 cfg_rcw_src = cfg_rcw_src1;
50 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
51
52 if (cfg_rcw_src == 0x44)
53 printf("QSPI vBank %d\n", CPLD_READ(vbank));
54 else if (cfg_rcw_src == 0x40)
55 puts("SD\n");
56 else
57 puts("Invalid setting of SW5\n");
58
59 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
60 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
61
62 puts("SERDES Reference Clocks:\n");
63 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
64 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
65
66 return 0;
67}
68
Mingkai Hud2396512016-09-07 18:47:28 +080069int board_init(void)
70{
71 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
72
Udit Agarwal22ec2382019-11-07 16:11:32 +000073#ifdef CONFIG_NXP_ESBC
Vinitha Pillai-B57223a47072e2017-03-23 13:48:18 +053074 /*
75 * In case of Secure Boot, the IBR configures the SMMU
76 * to allow only Secure transactions.
77 * SMMU must be reset in bypass mode.
78 * Set the ClientPD bit and Clear the USFCFG Bit
79 */
80 u32 val;
81 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
82 out_le32(SMMU_SCR0, val);
83 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
84 out_le32(SMMU_NSCR0, val);
85#endif
86
87#ifdef CONFIG_FSL_CAAM
88 sec_init();
89#endif
90
Mingkai Hud2396512016-09-07 18:47:28 +080091#ifdef CONFIG_FSL_LS_PPA
92 ppa_init();
93#endif
94
95 /* invert AQR105 IRQ pins polarity */
96 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
97
98 return 0;
99}
100
Hou Zhiqiang67b6d0a2016-12-09 16:09:01 +0800101int board_setup_core_volt(u32 vdd)
102{
103 bool en_0v9;
104
105 en_0v9 = (vdd == 900) ? true : false;
106 cpld_select_core_volt(en_0v9);
107
108 return 0;
109}
110
111int get_serdes_volt(void)
112{
113 return mc34vr500_get_sw_volt(SW4);
114}
115
116int set_serdes_volt(int svdd)
117{
118 return mc34vr500_set_sw_volt(SW4, svdd);
119}
120
121int power_init_board(void)
122{
123 int ret;
124
125 ret = power_mc34vr500_init(0);
126 if (ret)
127 return ret;
128
129 setup_chip_volt();
130
131 return 0;
132}
133
Mingkai Hud2396512016-09-07 18:47:28 +0800134void config_board_mux(void)
135{
136#ifdef CONFIG_HAS_FSL_XHCI_USB
137 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
138 u32 usb_pwrfault;
139
140 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
141 out_be32(&scfg->rcwpmuxcr0, 0x3300);
142 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
143 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
144 SCFG_USBPWRFAULT_USB3_SHIFT) |
145 (SCFG_USBPWRFAULT_DEDICATED <<
146 SCFG_USBPWRFAULT_USB2_SHIFT) |
147 (SCFG_USBPWRFAULT_SHARED <<
148 SCFG_USBPWRFAULT_USB1_SHIFT);
149 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
150#endif
151}
152
153#ifdef CONFIG_MISC_INIT_R
154int misc_init_r(void)
155{
156 config_board_mux();
157 return 0;
158}
159#endif
160
161int ft_board_setup(void *blob, bd_t *bd)
162{
163 u64 base[CONFIG_NR_DRAM_BANKS];
164 u64 size[CONFIG_NR_DRAM_BANKS];
165
166 /* fixup DT for the two DDR banks */
167 base[0] = gd->bd->bi_dram[0].start;
168 size[0] = gd->bd->bi_dram[0].size;
169 base[1] = gd->bd->bi_dram[1].start;
170 size[1] = gd->bd->bi_dram[1].size;
171
172 fdt_fixup_memory_banks(blob, base, size, 2);
173 ft_cpu_setup(blob, bd);
174
175#ifdef CONFIG_SYS_DPAA_FMAN
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300176#ifndef CONFIG_DM_ETH
Mingkai Hud2396512016-09-07 18:47:28 +0800177 fdt_fixup_fman_ethernet(blob);
178#endif
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300179#endif
Mingkai Hud2396512016-09-07 18:47:28 +0800180
Laurentiu Tudor512d13e2018-08-09 15:19:46 +0300181 fdt_fixup_icid(blob);
182
Mingkai Hud2396512016-09-07 18:47:28 +0800183 return 0;
184}
Sumit Gargc064fc72017-03-30 09:53:13 +0530185#endif