Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2018 Cisco Systems, Inc. |
Thomas Fitzsimmons | 06edafb | 2019-05-17 08:17:07 -0400 | [diff] [blame] | 4 | * (C) Copyright 2019 Synamedia |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 5 | * |
| 6 | * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> |
| 7 | */ |
| 8 | |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 12 | #include <time.h> |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 13 | #include <linux/types.h> |
| 14 | #include <common.h> |
Simon Glass | 313112a | 2019-08-01 09:46:46 -0600 | [diff] [blame] | 15 | #include <env.h> |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <asm/bootm.h> |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 18 | #include <mach/timer.h> |
| 19 | #include <mmc.h> |
| 20 | #include <fdtdec.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | #define BCMSTB_DATA_SECTION __attribute__((section(".data"))) |
| 25 | |
| 26 | struct bcmstb_boot_parameters bcmstb_boot_parameters BCMSTB_DATA_SECTION; |
| 27 | |
| 28 | phys_addr_t prior_stage_fdt_address BCMSTB_DATA_SECTION; |
| 29 | |
| 30 | union reg_value_union { |
| 31 | const char *data; |
| 32 | const phys_addr_t *address; |
| 33 | }; |
| 34 | |
| 35 | int board_init(void) |
| 36 | { |
| 37 | return 0; |
| 38 | } |
| 39 | |
| 40 | u32 get_board_rev(void) |
| 41 | { |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | void reset_cpu(ulong ignored) |
| 46 | { |
| 47 | } |
| 48 | |
| 49 | int print_cpuinfo(void) |
| 50 | { |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | int dram_init(void) |
| 55 | { |
Siva Durga Prasad Paladugu | b3d55ea | 2018-07-16 15:56:11 +0530 | [diff] [blame] | 56 | if (fdtdec_setup_mem_size_base() != 0) |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 57 | return -EINVAL; |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | int dram_init_banksize(void) |
| 63 | { |
| 64 | fdtdec_setup_memory_banksize(); |
| 65 | |
| 66 | /* |
| 67 | * On this SoC, U-Boot is running as an ELF file. Change the |
| 68 | * relocation address to CONFIG_SYS_TEXT_BASE, so that in |
| 69 | * setup_reloc, gd->reloc_off works out to 0, effectively |
| 70 | * disabling relocation. Otherwise U-Boot hangs in the setup |
| 71 | * instructions just before relocate_code in |
| 72 | * arch/arm/lib/crt0.S. |
| 73 | */ |
| 74 | gd->relocaddr = CONFIG_SYS_TEXT_BASE; |
| 75 | |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | void enable_caches(void) |
| 80 | { |
| 81 | /* |
| 82 | * This port assumes that the prior stage bootloader has |
| 83 | * enabled I-cache and D-cache already. Implementing this |
| 84 | * function silences the warning in the default function. |
| 85 | */ |
| 86 | } |
| 87 | |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 88 | int timer_init(void) |
| 89 | { |
| 90 | gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY); |
| 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | ulong get_tbclk(void) |
| 96 | { |
| 97 | return gd->arch.timer_rate_hz; |
| 98 | } |
| 99 | |
| 100 | uint64_t get_ticks(void) |
| 101 | { |
| 102 | gd->timebase_h = readl(BCMSTB_TIMER_HIGH); |
| 103 | gd->timebase_l = readl(BCMSTB_TIMER_LOW); |
| 104 | |
| 105 | return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l; |
| 106 | } |
| 107 | |
| 108 | int board_late_init(void) |
| 109 | { |
| 110 | debug("Arguments from prior stage bootloader:\n"); |
| 111 | debug("General Purpose Register 0: 0x%x\n", bcmstb_boot_parameters.r0); |
| 112 | debug("General Purpose Register 1: 0x%x\n", bcmstb_boot_parameters.r1); |
| 113 | debug("General Purpose Register 2: 0x%x\n", bcmstb_boot_parameters.r2); |
| 114 | debug("General Purpose Register 3: 0x%x\n", bcmstb_boot_parameters.r3); |
| 115 | debug("Stack Pointer Register: 0x%x\n", bcmstb_boot_parameters.sp); |
| 116 | debug("Link Register: 0x%x\n", bcmstb_boot_parameters.lr); |
| 117 | debug("Assuming timer frequency register at: 0x%p\n", |
| 118 | (void *)BCMSTB_TIMER_FREQUENCY); |
| 119 | debug("Read timer frequency (in Hz): %ld\n", gd->arch.timer_rate_hz); |
| 120 | debug("Prior stage provided DTB at: 0x%p\n", |
| 121 | (void *)prior_stage_fdt_address); |
| 122 | |
| 123 | /* |
| 124 | * Set fdtcontroladdr in the environment so that scripts can |
| 125 | * refer to it, for example, to reuse it for fdtaddr. |
| 126 | */ |
| 127 | env_set_hex("fdtcontroladdr", prior_stage_fdt_address); |
| 128 | |
| 129 | /* |
| 130 | * Do not set machid to the machine identifier value provided |
| 131 | * by the prior stage bootloader (bcmstb_boot_parameters.r1) |
| 132 | * because we're using a device tree to boot Linux. |
| 133 | */ |
| 134 | |
| 135 | return 0; |
| 136 | } |